thread_context.hh revision 2680
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_THREAD_CONTEXT_HH__ 32#define __CPU_THREAD_CONTEXT_HH__ 33 34#include "config/full_system.hh" 35#include "mem/request.hh" 36#include "sim/faults.hh" 37#include "sim/host.hh" 38#include "sim/serialize.hh" 39#include "sim/byteswap.hh" 40 41// @todo: Figure out a more architecture independent way to obtain the ITB and 42// DTB pointers. 43class AlphaDTB; 44class AlphaITB; 45class BaseCPU; 46class EndQuiesceEvent; 47class Event; 48class TranslatingPort; 49class FunctionalPort; 50class VirtualPort; 51class Process; 52class System; 53namespace Kernel { 54 class Statistics; 55}; 56 57/** 58 * ThreadContext is the external interface to all thread state for 59 * anything outside of the CPU. It provides all accessor methods to 60 * state that might be needed by external objects, ranging from 61 * register values to things such as kernel stats. It is an abstract 62 * base class; the CPU can create its own ThreadContext by either 63 * deriving from it, or using the templated ProxyThreadContext. 64 * 65 * The ThreadContext is slightly different than the ExecContext. The 66 * ThreadContext provides access to an individual thread's state; an 67 * ExecContext provides ISA access to the CPU (meaning it is 68 * implicitly multithreaded on MT systems). Additionally the 69 * ThreadState is an abstract class that exactly defines the 70 * interface; the ExecContext is a more implicit interface that must 71 * be implemented so that the ISA can access whatever state it needs. 72 */ 73class ThreadContext 74{ 75 protected: 76 typedef TheISA::RegFile RegFile; 77 typedef TheISA::MachInst MachInst; 78 typedef TheISA::IntReg IntReg; 79 typedef TheISA::FloatReg FloatReg; 80 typedef TheISA::FloatRegBits FloatRegBits; 81 typedef TheISA::MiscRegFile MiscRegFile; 82 typedef TheISA::MiscReg MiscReg; 83 public: 84 enum Status 85 { 86 /// Initialized but not running yet. All CPUs start in 87 /// this state, but most transition to Active on cycle 1. 88 /// In MP or SMT systems, non-primary contexts will stay 89 /// in this state until a thread is assigned to them. 90 Unallocated, 91 92 /// Running. Instructions should be executed only when 93 /// the context is in this state. 94 Active, 95 96 /// Temporarily inactive. Entered while waiting for 97 /// synchronization, etc. 98 Suspended, 99 100 /// Permanently shut down. Entered when target executes 101 /// m5exit pseudo-instruction. When all contexts enter 102 /// this state, the simulation will terminate. 103 Halted 104 }; 105 106 virtual ~ThreadContext() { }; 107 108 virtual BaseCPU *getCpuPtr() = 0; 109 110 virtual void setCpuId(int id) = 0; 111 112 virtual int readCpuId() = 0; 113 114#if FULL_SYSTEM 115 virtual System *getSystemPtr() = 0; 116 117 virtual AlphaITB *getITBPtr() = 0; 118 119 virtual AlphaDTB * getDTBPtr() = 0; 120 121 virtual Kernel::Statistics *getKernelStats() = 0; 122 123 virtual FunctionalPort *getPhysPort() = 0; 124 125 virtual VirtualPort *getVirtPort(ThreadContext *tc = NULL) = 0; 126 127 virtual void delVirtPort(VirtualPort *vp) = 0; 128#else 129 virtual TranslatingPort *getMemPort() = 0; 130 131 virtual Process *getProcessPtr() = 0; 132#endif 133 134 virtual Status status() const = 0; 135 136 virtual void setStatus(Status new_status) = 0; 137 138 /// Set the status to Active. Optional delay indicates number of 139 /// cycles to wait before beginning execution. 140 virtual void activate(int delay = 1) = 0; 141 142 /// Set the status to Suspended. 143 virtual void suspend() = 0; 144 145 /// Set the status to Unallocated. 146 virtual void deallocate() = 0; 147 148 /// Set the status to Halted. 149 virtual void halt() = 0; 150 151#if FULL_SYSTEM 152 virtual void dumpFuncProfile() = 0; 153#endif 154 155 virtual void takeOverFrom(ThreadContext *old_context) = 0; 156 157 virtual void regStats(const std::string &name) = 0; 158 159 virtual void serialize(std::ostream &os) = 0; 160 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 161 162#if FULL_SYSTEM 163 virtual EndQuiesceEvent *getQuiesceEvent() = 0; 164 165 // Not necessarily the best location for these... 166 // Having an extra function just to read these is obnoxious 167 virtual Tick readLastActivate() = 0; 168 virtual Tick readLastSuspend() = 0; 169 170 virtual void profileClear() = 0; 171 virtual void profileSample() = 0; 172#endif 173 174 virtual int getThreadNum() = 0; 175 176 // Also somewhat obnoxious. Really only used for the TLB fault. 177 // However, may be quite useful in SPARC. 178 virtual TheISA::MachInst getInst() = 0; 179 180 virtual void copyArchRegs(ThreadContext *tc) = 0; 181 182 virtual void clearArchRegs() = 0; 183 184 // 185 // New accessors for new decoder. 186 // 187 virtual uint64_t readIntReg(int reg_idx) = 0; 188 189 virtual FloatReg readFloatReg(int reg_idx, int width) = 0; 190 191 virtual FloatReg readFloatReg(int reg_idx) = 0; 192 193 virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0; 194 195 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 196 197 virtual void setIntReg(int reg_idx, uint64_t val) = 0; 198 199 virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0; 200 201 virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 202 203 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 204 205 virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0; 206 207 virtual uint64_t readPC() = 0; 208 209 virtual void setPC(uint64_t val) = 0; 210 211 virtual uint64_t readNextPC() = 0; 212 213 virtual void setNextPC(uint64_t val) = 0; 214 215 virtual uint64_t readNextNPC() = 0; 216 217 virtual void setNextNPC(uint64_t val) = 0; 218 219 virtual MiscReg readMiscReg(int misc_reg) = 0; 220 221 virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) = 0; 222 223 virtual Fault setMiscReg(int misc_reg, const MiscReg &val) = 0; 224 225 virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0; 226 227 // Also not necessarily the best location for these two. Hopefully will go 228 // away once we decide upon where st cond failures goes. 229 virtual unsigned readStCondFailures() = 0; 230 231 virtual void setStCondFailures(unsigned sc_failures) = 0; 232 233#if FULL_SYSTEM 234 virtual bool inPalMode() = 0; 235#endif 236 237 // Only really makes sense for old CPU model. Still could be useful though. 238 virtual bool misspeculating() = 0; 239 240#if !FULL_SYSTEM 241 virtual IntReg getSyscallArg(int i) = 0; 242 243 // used to shift args for indirect syscall 244 virtual void setSyscallArg(int i, IntReg val) = 0; 245 246 virtual void setSyscallReturn(SyscallReturn return_value) = 0; 247 248 249 // Same with st cond failures. 250 virtual Counter readFuncExeInst() = 0; 251#endif 252 253 virtual void changeRegFileContext(RegFile::ContextParam param, 254 RegFile::ContextVal val) = 0; 255}; 256 257template <class TC> 258class ProxyThreadContext : public ThreadContext 259{ 260 public: 261 ProxyThreadContext(TC *actual_tc) 262 { actualTC = actual_tc; } 263 264 private: 265 TC *actualTC; 266 267 public: 268 269 BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 270 271 void setCpuId(int id) { actualTC->setCpuId(id); } 272 273 int readCpuId() { return actualTC->readCpuId(); } 274 275#if FULL_SYSTEM 276 System *getSystemPtr() { return actualTC->getSystemPtr(); } 277 278 AlphaITB *getITBPtr() { return actualTC->getITBPtr(); } 279 280 AlphaDTB *getDTBPtr() { return actualTC->getDTBPtr(); } 281 282 Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); } 283 284 FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); } 285 286 VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return actualTC->getVirtPort(tc); } 287 288 void delVirtPort(VirtualPort *vp) { return actualTC->delVirtPort(vp); } 289#else 290 TranslatingPort *getMemPort() { return actualTC->getMemPort(); } 291 292 Process *getProcessPtr() { return actualTC->getProcessPtr(); } 293#endif 294 295 Status status() const { return actualTC->status(); } 296 297 void setStatus(Status new_status) { actualTC->setStatus(new_status); } 298 299 /// Set the status to Active. Optional delay indicates number of 300 /// cycles to wait before beginning execution. 301 void activate(int delay = 1) { actualTC->activate(delay); } 302 303 /// Set the status to Suspended. 304 void suspend() { actualTC->suspend(); } 305 306 /// Set the status to Unallocated. 307 void deallocate() { actualTC->deallocate(); } 308 309 /// Set the status to Halted. 310 void halt() { actualTC->halt(); } 311 312#if FULL_SYSTEM 313 void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 314#endif 315 316 void takeOverFrom(ThreadContext *oldContext) 317 { actualTC->takeOverFrom(oldContext); } 318 319 void regStats(const std::string &name) { actualTC->regStats(name); } 320 321 void serialize(std::ostream &os) { actualTC->serialize(os); } 322 void unserialize(Checkpoint *cp, const std::string §ion) 323 { actualTC->unserialize(cp, section); } 324 325#if FULL_SYSTEM 326 EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 327 328 Tick readLastActivate() { return actualTC->readLastActivate(); } 329 Tick readLastSuspend() { return actualTC->readLastSuspend(); } 330 331 void profileClear() { return actualTC->profileClear(); } 332 void profileSample() { return actualTC->profileSample(); } 333#endif 334 335 int getThreadNum() { return actualTC->getThreadNum(); } 336 337 // @todo: Do I need this? 338 MachInst getInst() { return actualTC->getInst(); } 339 340 // @todo: Do I need this? 341 void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 342 343 void clearArchRegs() { actualTC->clearArchRegs(); } 344 345 // 346 // New accessors for new decoder. 347 // 348 uint64_t readIntReg(int reg_idx) 349 { return actualTC->readIntReg(reg_idx); } 350 351 FloatReg readFloatReg(int reg_idx, int width) 352 { return actualTC->readFloatReg(reg_idx, width); } 353 354 FloatReg readFloatReg(int reg_idx) 355 { return actualTC->readFloatReg(reg_idx); } 356 357 FloatRegBits readFloatRegBits(int reg_idx, int width) 358 { return actualTC->readFloatRegBits(reg_idx, width); } 359 360 FloatRegBits readFloatRegBits(int reg_idx) 361 { return actualTC->readFloatRegBits(reg_idx); } 362 363 void setIntReg(int reg_idx, uint64_t val) 364 { actualTC->setIntReg(reg_idx, val); } 365 366 void setFloatReg(int reg_idx, FloatReg val, int width) 367 { actualTC->setFloatReg(reg_idx, val, width); } 368 369 void setFloatReg(int reg_idx, FloatReg val) 370 { actualTC->setFloatReg(reg_idx, val); } 371 372 void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 373 { actualTC->setFloatRegBits(reg_idx, val, width); } 374 375 void setFloatRegBits(int reg_idx, FloatRegBits val) 376 { actualTC->setFloatRegBits(reg_idx, val); } 377 378 uint64_t readPC() { return actualTC->readPC(); } 379 380 void setPC(uint64_t val) { actualTC->setPC(val); } 381 382 uint64_t readNextPC() { return actualTC->readNextPC(); } 383 384 void setNextPC(uint64_t val) { actualTC->setNextPC(val); } 385 386 uint64_t readNextNPC() { return actualTC->readNextNPC(); } 387 388 void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); } 389 390 MiscReg readMiscReg(int misc_reg) 391 { return actualTC->readMiscReg(misc_reg); } 392 393 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) 394 { return actualTC->readMiscRegWithEffect(misc_reg, fault); } 395 396 Fault setMiscReg(int misc_reg, const MiscReg &val) 397 { return actualTC->setMiscReg(misc_reg, val); } 398 399 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) 400 { return actualTC->setMiscRegWithEffect(misc_reg, val); } 401 402 unsigned readStCondFailures() 403 { return actualTC->readStCondFailures(); } 404 405 void setStCondFailures(unsigned sc_failures) 406 { actualTC->setStCondFailures(sc_failures); } 407#if FULL_SYSTEM 408 bool inPalMode() { return actualTC->inPalMode(); } 409#endif 410 411 // @todo: Fix this! 412 bool misspeculating() { return actualTC->misspeculating(); } 413 414#if !FULL_SYSTEM 415 IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); } 416 417 // used to shift args for indirect syscall 418 void setSyscallArg(int i, IntReg val) 419 { actualTC->setSyscallArg(i, val); } 420 421 void setSyscallReturn(SyscallReturn return_value) 422 { actualTC->setSyscallReturn(return_value); } 423 424 425 Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 426#endif 427 428 void changeRegFileContext(RegFile::ContextParam param, 429 RegFile::ContextVal val) 430 { 431 actualTC->changeRegFileContext(param, val); 432 } 433}; 434 435#endif 436