thread_context.hh revision 2252
1/*
2 * Copyright (c) 2001-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __CPU_EXEC_CONTEXT_HH__
30#define __CPU_EXEC_CONTEXT_HH__
31
32#include "config/full_system.hh"
33#include "mem/functional/functional.hh"
34#include "mem/mem_req.hh"
35#include "sim/eventq.hh"
36#include "sim/host.hh"
37#include "sim/serialize.hh"
38#include "arch/isa_traits.hh"
39//#include "arch/isa_registers.hh"
40#include "sim/byteswap.hh"
41
42// forward declaration: see functional_memory.hh
43class FunctionalMemory;
44class PhysicalMemory;
45class BaseCPU;
46
47#if FULL_SYSTEM
48
49#include "sim/system.hh"
50#include "arch/tlb.hh"
51
52class FunctionProfile;
53class ProfileNode;
54class MemoryController;
55namespace Kernel { class Binning; class Statistics; }
56
57#else // !FULL_SYSTEM
58
59#include "sim/process.hh"
60
61#endif // FULL_SYSTEM
62
63//
64// The ExecContext object represents a functional context for
65// instruction execution.  It incorporates everything required for
66// architecture-level functional simulation of a single thread.
67//
68
69class ExecContext
70{
71  protected:
72    typedef TheISA::RegFile RegFile;
73    typedef TheISA::MachInst MachInst;
74    typedef TheISA::MiscRegFile MiscRegFile;
75    typedef TheISA::MiscReg MiscReg;
76  public:
77    enum Status
78    {
79        /// Initialized but not running yet.  All CPUs start in
80        /// this state, but most transition to Active on cycle 1.
81        /// In MP or SMT systems, non-primary contexts will stay
82        /// in this state until a thread is assigned to them.
83        Unallocated,
84
85        /// Running.  Instructions should be executed only when
86        /// the context is in this state.
87        Active,
88
89        /// Temporarily inactive.  Entered while waiting for
90        /// initialization,synchronization, etc.
91        Suspended,
92
93        /// Permanently shut down.  Entered when target executes
94        /// m5exit pseudo-instruction.  When all contexts enter
95        /// this state, the simulation will terminate.
96        Halted
97    };
98
99  private:
100    Status _status;
101
102  public:
103    Status status() const { return _status; }
104
105    void setStatus(Status newStatus) { _status = newStatus; }
106
107    /// Set the status to Active.  Optional delay indicates number of
108    /// cycles to wait before beginning execution.
109    void activate(int delay = 1);
110
111    /// Set the status to Suspended.
112    void suspend();
113
114    /// Set the status to Unallocated.
115    void deallocate();
116
117    /// Set the status to Halted.
118    void halt();
119
120  public:
121    RegFile regs;	// correct-path register context
122
123    // pointer to CPU associated with this context
124    BaseCPU *cpu;
125
126    // Current instruction
127    MachInst inst;
128
129    // Index of hardware thread context on the CPU that this represents.
130    int thread_num;
131
132    // ID of this context w.r.t. the System or Process object to which
133    // it belongs.  For full-system mode, this is the system CPU ID.
134    int cpu_id;
135
136    Tick lastActivate;
137    Tick lastSuspend;
138
139#if FULL_SYSTEM
140    FunctionalMemory *mem;
141    AlphaITB *itb;
142    AlphaDTB *dtb;
143    System *system;
144
145    // the following two fields are redundant, since we can always
146    // look them up through the system pointer, but we'll leave them
147    // here for now for convenience
148    MemoryController *memctrl;
149    PhysicalMemory *physmem;
150
151    Kernel::Binning *kernelBinning;
152    Kernel::Statistics *kernelStats;
153    bool bin;
154    bool fnbin;
155
156    FunctionProfile *profile;
157    ProfileNode *profileNode;
158    Addr profilePC;
159    void dumpFuncProfile();
160
161    /** Event for timing out quiesce instruction */
162    struct EndQuiesceEvent : public Event
163    {
164        /** A pointer to the execution context that is quiesced */
165        ExecContext *xc;
166
167        EndQuiesceEvent(ExecContext *_xc);
168
169        /** Event process to occur at interrupt*/
170        virtual void process();
171
172        /** Event description */
173        virtual const char *description();
174    };
175    EndQuiesceEvent quiesceEvent;
176
177#else
178    Process *process;
179
180    FunctionalMemory *mem;	// functional storage for process address space
181
182    // Address space ID.  Note that this is used for TIMING cache
183    // simulation only; all functional memory accesses should use
184    // one of the FunctionalMemory pointers above.
185    short asid;
186
187#endif
188
189    /**
190     * Temporary storage to pass the source address from copy_load to
191     * copy_store.
192     * @todo Remove this temporary when we have a better way to do it.
193     */
194    Addr copySrcAddr;
195    /**
196     * Temp storage for the physical source address of a copy.
197     * @todo Remove this temporary when we have a better way to do it.
198     */
199    Addr copySrcPhysAddr;
200
201
202    /*
203     * number of executed instructions, for matching with syscall trace
204     * points in EIO files.
205     */
206    Counter func_exe_inst;
207
208    //
209    // Count failed store conditionals so we can warn of apparent
210    // application deadlock situations.
211    unsigned storeCondFailures;
212
213    // constructor: initialize context from given process structure
214#if FULL_SYSTEM
215    ExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
216                AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem);
217#else
218    ExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
219    ExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem,
220                int _asid);
221#endif
222    virtual ~ExecContext();
223
224    virtual void takeOverFrom(ExecContext *oldContext);
225
226    void regStats(const std::string &name);
227
228    void serialize(std::ostream &os);
229    void unserialize(Checkpoint *cp, const std::string &section);
230
231#if FULL_SYSTEM
232    bool validInstAddr(Addr addr) { return true; }
233    bool validDataAddr(Addr addr) { return true; }
234    int getInstAsid() { return regs.instAsid(); }
235    int getDataAsid() { return regs.dataAsid(); }
236
237    Fault translateInstReq(MemReqPtr &req)
238    {
239        return itb->translate(req);
240    }
241
242    Fault translateDataReadReq(MemReqPtr &req)
243    {
244        return dtb->translate(req, false);
245    }
246
247    Fault translateDataWriteReq(MemReqPtr &req)
248    {
249        return dtb->translate(req, true);
250    }
251
252#else
253    bool validInstAddr(Addr addr)
254    { return process->validInstAddr(addr); }
255
256    bool validDataAddr(Addr addr)
257    { return process->validDataAddr(addr); }
258
259    int getInstAsid() { return asid; }
260    int getDataAsid() { return asid; }
261
262    Fault dummyTranslation(MemReqPtr &req)
263    {
264#if 0
265        assert((req->vaddr >> 48 & 0xffff) == 0);
266#endif
267
268        // put the asid in the upper 16 bits of the paddr
269        req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
270        req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
271        return NoFault;
272    }
273    Fault translateInstReq(MemReqPtr &req)
274    {
275        return dummyTranslation(req);
276    }
277    Fault translateDataReadReq(MemReqPtr &req)
278    {
279        return dummyTranslation(req);
280    }
281    Fault translateDataWriteReq(MemReqPtr &req)
282    {
283        return dummyTranslation(req);
284    }
285
286#endif
287
288    template <class T>
289    Fault read(MemReqPtr &req, T &data)
290    {
291#if FULL_SYSTEM && defined(TARGET_ALPHA)
292        if (req->flags & LOCKED) {
293            MiscRegFile *cregs = &req->xc->regs.miscRegs;
294            cregs->setReg(TheISA::Lock_Addr_DepTag, req->paddr);
295            cregs->setReg(TheISA::Lock_Flag_DepTag, true);
296        }
297#endif
298
299        Fault error;
300        error = mem->read(req, data);
301        data = LittleEndianGuest::gtoh(data);
302        return error;
303    }
304
305    template <class T>
306    Fault write(MemReqPtr &req, T &data)
307    {
308#if FULL_SYSTEM && defined(TARGET_ALPHA)
309
310        MiscRegFile *cregs;
311
312        // If this is a store conditional, act appropriately
313        if (req->flags & LOCKED) {
314            cregs = &req->xc->regs.miscRegs;
315
316            if (req->flags & UNCACHEABLE) {
317                // Don't update result register (see stq_c in isa_desc)
318                req->result = 2;
319                req->xc->storeCondFailures = 0;//Needed? [RGD]
320            } else {
321                bool lock_flag = cregs->readReg(TheISA::Lock_Flag_DepTag);
322                Addr lock_addr = cregs->readReg(TheISA::Lock_Addr_DepTag);
323                req->result = lock_flag;
324                if (!lock_flag ||
325                    ((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
326                    cregs->setReg(TheISA::Lock_Flag_DepTag, false);
327                    if (((++req->xc->storeCondFailures) % 100000) == 0) {
328                        std::cerr << "Warning: "
329                                  << req->xc->storeCondFailures
330                                  << " consecutive store conditional failures "
331                                  << "on cpu " << req->xc->cpu_id
332                                  << std::endl;
333                    }
334                    return NoFault;
335                }
336                else req->xc->storeCondFailures = 0;
337            }
338        }
339
340        // Need to clear any locked flags on other proccessors for
341        // this address.  Only do this for succsful Store Conditionals
342        // and all other stores (WH64?).  Unsuccessful Store
343        // Conditionals would have returned above, and wouldn't fall
344        // through.
345        for (int i = 0; i < system->execContexts.size(); i++){
346            cregs = &system->execContexts[i]->regs.miscRegs;
347            if ((cregs->readReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
348                (req->paddr & ~0xf)) {
349                cregs->setReg(TheISA::Lock_Flag_DepTag, false);
350            }
351        }
352
353#endif
354        return mem->write(req, (T)LittleEndianGuest::htog(data));
355    }
356
357    virtual bool misspeculating();
358
359
360    MachInst getInst() { return inst; }
361
362    void setInst(MachInst new_inst)
363    {
364        inst = new_inst;
365    }
366
367    Fault instRead(MemReqPtr &req)
368    {
369        return mem->read(req, inst);
370    }
371
372    //
373    // New accessors for new decoder.
374    //
375    uint64_t readIntReg(int reg_idx)
376    {
377        return regs.intRegFile[reg_idx];
378    }
379
380    float readFloatRegSingle(int reg_idx)
381    {
382        return (float)regs.floatRegFile.d[reg_idx];
383    }
384
385    double readFloatRegDouble(int reg_idx)
386    {
387        return regs.floatRegFile.d[reg_idx];
388    }
389
390    uint64_t readFloatRegInt(int reg_idx)
391    {
392        return regs.floatRegFile.q[reg_idx];
393    }
394
395    void setIntReg(int reg_idx, uint64_t val)
396    {
397        regs.intRegFile[reg_idx] = val;
398    }
399
400    void setFloatRegSingle(int reg_idx, float val)
401    {
402        regs.floatRegFile.d[reg_idx] = (double)val;
403    }
404
405    void setFloatRegDouble(int reg_idx, double val)
406    {
407        regs.floatRegFile.d[reg_idx] = val;
408    }
409
410    void setFloatRegInt(int reg_idx, uint64_t val)
411    {
412        regs.floatRegFile.q[reg_idx] = val;
413    }
414
415    uint64_t readPC()
416    {
417        return regs.pc;
418    }
419
420    void setNextPC(uint64_t val)
421    {
422        regs.npc = val;
423    }
424
425    uint64_t readNextNPC()
426    {
427        return regs.nnpc;
428    }
429
430    void setNextNPC(uint64_t val)
431    {
432        regs.nnpc = val;
433    }
434
435
436    MiscReg readMiscReg(int misc_reg)
437    {
438        return regs.miscRegs.readReg(misc_reg);
439    }
440
441    MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
442    {
443        return regs.miscRegs.readRegWithEffect(misc_reg, fault, this);
444    }
445
446    Fault setMiscReg(int misc_reg, const MiscReg &val)
447    {
448        return regs.miscRegs.setReg(misc_reg, val);
449    }
450
451    Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
452    {
453        return regs.miscRegs.setRegWithEffect(misc_reg, val, this);
454    }
455
456#if FULL_SYSTEM
457    int readIntrFlag() { return regs.intrflag; }
458    void setIntrFlag(int val) { regs.intrflag = val; }
459    Fault hwrei();
460    bool inPalMode() { return AlphaISA::PcPAL(regs.pc); }
461    bool simPalCheck(int palFunc);
462#endif
463
464#if !FULL_SYSTEM
465    TheISA::IntReg getSyscallArg(int i)
466    {
467        return regs.intRegFile[TheISA::ArgumentReg0 + i];
468    }
469
470    // used to shift args for indirect syscall
471    void setSyscallArg(int i, TheISA::IntReg val)
472    {
473        regs.intRegFile[TheISA::ArgumentReg0 + i] = val;
474    }
475
476    void setSyscallReturn(SyscallReturn return_value)
477    {
478        // check for error condition.  Alpha syscall convention is to
479        // indicate success/failure in reg a3 (r19) and put the
480        // return value itself in the standard return value reg (v0).
481        const int RegA3 = 19;	// only place this is used
482        if (return_value.successful()) {
483            // no error
484            regs.intRegFile[RegA3] = 0;
485            regs.intRegFile[TheISA::ReturnValueReg] = return_value.value();
486        } else {
487            // got an error, return details
488            regs.intRegFile[RegA3] = (TheISA::IntReg) -1;
489            regs.intRegFile[TheISA::ReturnValueReg] = -return_value.value();
490        }
491    }
492
493    void syscall()
494    {
495        process->syscall(this);
496    }
497#endif
498};
499
500
501// for non-speculative execution context, spec_mode is always false
502inline bool
503ExecContext::misspeculating()
504{
505    return false;
506}
507
508#endif // __CPU_EXEC_CONTEXT_HH__
509