thread_context.hh revision 8733
12SN/A/* 28733Sgeoffrey.blake@arm.com * Copyright (c) 2011 ARM Limited 38733Sgeoffrey.blake@arm.com * All rights reserved 48733Sgeoffrey.blake@arm.com * 58733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 68733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 78733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 88733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 98733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 108733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 118733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 128733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 138733Sgeoffrey.blake@arm.com * 142190SN/A * Copyright (c) 2006 The Regents of The University of Michigan 152SN/A * All rights reserved. 162SN/A * 172SN/A * Redistribution and use in source and binary forms, with or without 182SN/A * modification, are permitted provided that the following conditions are 192SN/A * met: redistributions of source code must retain the above copyright 202SN/A * notice, this list of conditions and the following disclaimer; 212SN/A * redistributions in binary form must reproduce the above copyright 222SN/A * notice, this list of conditions and the following disclaimer in the 232SN/A * documentation and/or other materials provided with the distribution; 242SN/A * neither the name of the copyright holders nor the names of its 252SN/A * contributors may be used to endorse or promote products derived from 262SN/A * this software without specific prior written permission. 272SN/A * 282SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665SN/A * 402665SN/A * Authors: Kevin Lim 412SN/A */ 422SN/A 432680Sktlim@umich.edu#ifndef __CPU_THREAD_CONTEXT_HH__ 442680Sktlim@umich.edu#define __CPU_THREAD_CONTEXT_HH__ 452SN/A 468229Snate@binkert.org#include <iostream> 477680Sgblack@eecs.umich.edu#include <string> 487680Sgblack@eecs.umich.edu 496329Sgblack@eecs.umich.edu#include "arch/registers.hh" 503453Sgblack@eecs.umich.edu#include "arch/types.hh" 516216Snate@binkert.org#include "base/types.hh" 521858SN/A#include "config/full_system.hh" 536658Snate@binkert.org#include "config/the_isa.hh" 548733Sgeoffrey.blake@arm.com#include "config/use_checker.hh" 552SN/A 562190SN/A// @todo: Figure out a more architecture independent way to obtain the ITB and 572190SN/A// DTB pointers. 583453Sgblack@eecs.umich.edunamespace TheISA 593453Sgblack@eecs.umich.edu{ 606022Sgblack@eecs.umich.edu class TLB; 613453Sgblack@eecs.umich.edu} 622190SN/Aclass BaseCPU; 637680Sgblack@eecs.umich.educlass Checkpoint; 648541Sgblack@eecs.umich.educlass Decoder; 652313SN/Aclass EndQuiesceEvent; 668706Sandreas.hansson@arm.comclass SETranslatingPortProxy; 678706Sandreas.hansson@arm.comclass FSTranslatingPortProxy; 688706Sandreas.hansson@arm.comclass PortProxy; 692190SN/Aclass Process; 702190SN/Aclass System; 713548Sgblack@eecs.umich.edunamespace TheISA { 723548Sgblack@eecs.umich.edu namespace Kernel { 733548Sgblack@eecs.umich.edu class Statistics; 743548Sgblack@eecs.umich.edu }; 752330SN/A}; 762SN/A 772680Sktlim@umich.edu/** 782680Sktlim@umich.edu * ThreadContext is the external interface to all thread state for 792680Sktlim@umich.edu * anything outside of the CPU. It provides all accessor methods to 802680Sktlim@umich.edu * state that might be needed by external objects, ranging from 812680Sktlim@umich.edu * register values to things such as kernel stats. It is an abstract 822680Sktlim@umich.edu * base class; the CPU can create its own ThreadContext by either 832680Sktlim@umich.edu * deriving from it, or using the templated ProxyThreadContext. 842680Sktlim@umich.edu * 852680Sktlim@umich.edu * The ThreadContext is slightly different than the ExecContext. The 862680Sktlim@umich.edu * ThreadContext provides access to an individual thread's state; an 872680Sktlim@umich.edu * ExecContext provides ISA access to the CPU (meaning it is 882682Sktlim@umich.edu * implicitly multithreaded on SMT systems). Additionally the 892680Sktlim@umich.edu * ThreadState is an abstract class that exactly defines the 902680Sktlim@umich.edu * interface; the ExecContext is a more implicit interface that must 912680Sktlim@umich.edu * be implemented so that the ISA can access whatever state it needs. 922680Sktlim@umich.edu */ 932680Sktlim@umich.educlass ThreadContext 942SN/A{ 952107SN/A protected: 962107SN/A typedef TheISA::MachInst MachInst; 972190SN/A typedef TheISA::IntReg IntReg; 982455SN/A typedef TheISA::FloatReg FloatReg; 992455SN/A typedef TheISA::FloatRegBits FloatRegBits; 1002159SN/A typedef TheISA::MiscReg MiscReg; 1012SN/A public: 1026029Ssteve.reinhardt@amd.com 103246SN/A enum Status 104246SN/A { 105246SN/A /// Running. Instructions should be executed only when 106246SN/A /// the context is in this state. 107246SN/A Active, 108246SN/A 109246SN/A /// Temporarily inactive. Entered while waiting for 1102190SN/A /// synchronization, etc. 111246SN/A Suspended, 112246SN/A 113246SN/A /// Permanently shut down. Entered when target executes 114246SN/A /// m5exit pseudo-instruction. When all contexts enter 115246SN/A /// this state, the simulation will terminate. 116246SN/A Halted 117246SN/A }; 1182SN/A 1192680Sktlim@umich.edu virtual ~ThreadContext() { }; 1202423SN/A 1212190SN/A virtual BaseCPU *getCpuPtr() = 0; 122180SN/A 1235712Shsul@eecs.umich.edu virtual int cpuId() = 0; 1242190SN/A 1255715Shsul@eecs.umich.edu virtual int threadId() = 0; 1265715Shsul@eecs.umich.edu 1275715Shsul@eecs.umich.edu virtual void setThreadId(int id) = 0; 1285714Shsul@eecs.umich.edu 1295714Shsul@eecs.umich.edu virtual int contextId() = 0; 1305714Shsul@eecs.umich.edu 1315714Shsul@eecs.umich.edu virtual void setContextId(int id) = 0; 1325714Shsul@eecs.umich.edu 1336022Sgblack@eecs.umich.edu virtual TheISA::TLB *getITBPtr() = 0; 1342190SN/A 1356022Sgblack@eecs.umich.edu virtual TheISA::TLB *getDTBPtr() = 0; 1362521SN/A 1378733Sgeoffrey.blake@arm.com#if USE_CHECKER 1388733Sgeoffrey.blake@arm.com virtual BaseCPU *getCheckerCpuPtr() = 0; 1398733Sgeoffrey.blake@arm.com#endif 1408733Sgeoffrey.blake@arm.com 1418541Sgblack@eecs.umich.edu virtual Decoder *getDecoderPtr() = 0; 1428541Sgblack@eecs.umich.edu 1434997Sgblack@eecs.umich.edu virtual System *getSystemPtr() = 0; 1444997Sgblack@eecs.umich.edu 1455803Snate@binkert.org#if FULL_SYSTEM 1463548Sgblack@eecs.umich.edu virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 1472654SN/A 1488706Sandreas.hansson@arm.com virtual PortProxy* getPhysProxy() = 0; 1492521SN/A 1508706Sandreas.hansson@arm.com virtual FSTranslatingPortProxy* getVirtProxy() = 0; 1513673Srdreslin@umich.edu 1528706Sandreas.hansson@arm.com /** 1538706Sandreas.hansson@arm.com * Initialise the physical and virtual port proxies and tie them to 1548706Sandreas.hansson@arm.com * the data port of the CPU. 1558706Sandreas.hansson@arm.com * 1568706Sandreas.hansson@arm.com * tc ThreadContext for the virtual-to-physical translation 1578706Sandreas.hansson@arm.com */ 1588706Sandreas.hansson@arm.com virtual void initMemProxies(ThreadContext *tc) = 0; 1592190SN/A#else 1608706Sandreas.hansson@arm.com virtual SETranslatingPortProxy *getMemProxy() = 0; 1612518SN/A 1622190SN/A virtual Process *getProcessPtr() = 0; 1632190SN/A#endif 1642190SN/A 1652190SN/A virtual Status status() const = 0; 1662159SN/A 1672235SN/A virtual void setStatus(Status new_status) = 0; 1682103SN/A 169393SN/A /// Set the status to Active. Optional delay indicates number of 170393SN/A /// cycles to wait before beginning execution. 1712190SN/A virtual void activate(int delay = 1) = 0; 172393SN/A 173393SN/A /// Set the status to Suspended. 1745250Sksewell@umich.edu virtual void suspend(int delay = 0) = 0; 175393SN/A 176393SN/A /// Set the status to Halted. 1775250Sksewell@umich.edu virtual void halt(int delay = 0) = 0; 1782159SN/A 1792159SN/A#if FULL_SYSTEM 1802190SN/A virtual void dumpFuncProfile() = 0; 1812159SN/A#endif 1822159SN/A 1832680Sktlim@umich.edu virtual void takeOverFrom(ThreadContext *old_context) = 0; 1842159SN/A 1852190SN/A virtual void regStats(const std::string &name) = 0; 1862159SN/A 1872190SN/A virtual void serialize(std::ostream &os) = 0; 1882190SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 1892159SN/A 1902235SN/A#if FULL_SYSTEM 1912313SN/A virtual EndQuiesceEvent *getQuiesceEvent() = 0; 1922235SN/A 1932235SN/A // Not necessarily the best location for these... 1942235SN/A // Having an extra function just to read these is obnoxious 1952235SN/A virtual Tick readLastActivate() = 0; 1962235SN/A virtual Tick readLastSuspend() = 0; 1972254SN/A 1982254SN/A virtual void profileClear() = 0; 1992254SN/A virtual void profileSample() = 0; 2002235SN/A#endif 2012235SN/A 2022680Sktlim@umich.edu virtual void copyArchRegs(ThreadContext *tc) = 0; 2032159SN/A 2042190SN/A virtual void clearArchRegs() = 0; 2052159SN/A 2062159SN/A // 2072159SN/A // New accessors for new decoder. 2082159SN/A // 2092190SN/A virtual uint64_t readIntReg(int reg_idx) = 0; 2102159SN/A 2112455SN/A virtual FloatReg readFloatReg(int reg_idx) = 0; 2122159SN/A 2132455SN/A virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 2142159SN/A 2152190SN/A virtual void setIntReg(int reg_idx, uint64_t val) = 0; 2162159SN/A 2172455SN/A virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 2182159SN/A 2192455SN/A virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 2202455SN/A 2217720Sgblack@eecs.umich.edu virtual TheISA::PCState pcState() = 0; 2222159SN/A 2237720Sgblack@eecs.umich.edu virtual void pcState(const TheISA::PCState &val) = 0; 2242159SN/A 2258733Sgeoffrey.blake@arm.com#if USE_CHECKER 2268733Sgeoffrey.blake@arm.com virtual void pcStateNoRecord(const TheISA::PCState &val) = 0; 2278733Sgeoffrey.blake@arm.com#endif 2288733Sgeoffrey.blake@arm.com 2297720Sgblack@eecs.umich.edu virtual Addr instAddr() = 0; 2302159SN/A 2317720Sgblack@eecs.umich.edu virtual Addr nextInstAddr() = 0; 2322159SN/A 2337720Sgblack@eecs.umich.edu virtual MicroPC microPC() = 0; 2345260Sksewell@umich.edu 2354172Ssaidi@eecs.umich.edu virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; 2364172Ssaidi@eecs.umich.edu 2372190SN/A virtual MiscReg readMiscReg(int misc_reg) = 0; 2382159SN/A 2394172Ssaidi@eecs.umich.edu virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; 2402190SN/A 2413468Sgblack@eecs.umich.edu virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 2422190SN/A 2436313Sgblack@eecs.umich.edu virtual int flattenIntIndex(int reg) = 0; 2446313Sgblack@eecs.umich.edu virtual int flattenFloatIndex(int reg) = 0; 2456313Sgblack@eecs.umich.edu 2466221Snate@binkert.org virtual uint64_t 2476221Snate@binkert.org readRegOtherThread(int misc_reg, ThreadID tid) 2486221Snate@binkert.org { 2496221Snate@binkert.org return 0; 2506221Snate@binkert.org } 2514661Sksewell@umich.edu 2526221Snate@binkert.org virtual void 2536221Snate@binkert.org setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid) 2546221Snate@binkert.org { 2556221Snate@binkert.org } 2564661Sksewell@umich.edu 2572235SN/A // Also not necessarily the best location for these two. Hopefully will go 2582235SN/A // away once we decide upon where st cond failures goes. 2592190SN/A virtual unsigned readStCondFailures() = 0; 2602190SN/A 2612190SN/A virtual void setStCondFailures(unsigned sc_failures) = 0; 2622159SN/A 2632235SN/A // Only really makes sense for old CPU model. Still could be useful though. 2642190SN/A virtual bool misspeculating() = 0; 2652190SN/A 2662159SN/A#if !FULL_SYSTEM 2672235SN/A // Same with st cond failures. 2682190SN/A virtual Counter readFuncExeInst() = 0; 2692834Sksewell@umich.edu 2704111Sgblack@eecs.umich.edu virtual void syscall(int64_t callnum) = 0; 2714111Sgblack@eecs.umich.edu 2722834Sksewell@umich.edu // This function exits the thread context in the CPU and returns 2732834Sksewell@umich.edu // 1 if the CPU has no more active threads (meaning it's OK to exit); 2742834Sksewell@umich.edu // Used in syscall-emulation mode when a thread calls the exit syscall. 2752834Sksewell@umich.edu virtual int exit() { return 1; }; 2762159SN/A#endif 2772525SN/A 2785217Ssaidi@eecs.umich.edu /** function to compare two thread contexts (for debugging) */ 2795217Ssaidi@eecs.umich.edu static void compare(ThreadContext *one, ThreadContext *two); 2802159SN/A}; 2812159SN/A 2822682Sktlim@umich.edu/** 2832682Sktlim@umich.edu * ProxyThreadContext class that provides a way to implement a 2842682Sktlim@umich.edu * ThreadContext without having to derive from it. ThreadContext is an 2852682Sktlim@umich.edu * abstract class, so anything that derives from it and uses its 2862682Sktlim@umich.edu * interface will pay the overhead of virtual function calls. This 2872682Sktlim@umich.edu * class is created to enable a user-defined Thread object to be used 2882682Sktlim@umich.edu * wherever ThreadContexts are used, without paying the overhead of 2892682Sktlim@umich.edu * virtual function calls when it is used by itself. See 2902682Sktlim@umich.edu * simple_thread.hh for an example of this. 2912682Sktlim@umich.edu */ 2922680Sktlim@umich.edutemplate <class TC> 2932680Sktlim@umich.educlass ProxyThreadContext : public ThreadContext 2942190SN/A{ 2952190SN/A public: 2962680Sktlim@umich.edu ProxyThreadContext(TC *actual_tc) 2972680Sktlim@umich.edu { actualTC = actual_tc; } 2982159SN/A 2992190SN/A private: 3002680Sktlim@umich.edu TC *actualTC; 3012SN/A 3022SN/A public: 3032SN/A 3042680Sktlim@umich.edu BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 3052SN/A 3065712Shsul@eecs.umich.edu int cpuId() { return actualTC->cpuId(); } 3072SN/A 3085715Shsul@eecs.umich.edu int threadId() { return actualTC->threadId(); } 3095715Shsul@eecs.umich.edu 3105715Shsul@eecs.umich.edu void setThreadId(int id) { return actualTC->setThreadId(id); } 3115714Shsul@eecs.umich.edu 3125714Shsul@eecs.umich.edu int contextId() { return actualTC->contextId(); } 3135714Shsul@eecs.umich.edu 3145714Shsul@eecs.umich.edu void setContextId(int id) { actualTC->setContextId(id); } 3155714Shsul@eecs.umich.edu 3166022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 3171917SN/A 3186022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 3192521SN/A 3208733Sgeoffrey.blake@arm.com#if USE_CHECKER 3218733Sgeoffrey.blake@arm.com BaseCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); } 3228733Sgeoffrey.blake@arm.com#endif 3238733Sgeoffrey.blake@arm.com 3248541Sgblack@eecs.umich.edu Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); } 3258541Sgblack@eecs.umich.edu 3264997Sgblack@eecs.umich.edu System *getSystemPtr() { return actualTC->getSystemPtr(); } 3274997Sgblack@eecs.umich.edu 3285803Snate@binkert.org#if FULL_SYSTEM 3293548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *getKernelStats() 3303548Sgblack@eecs.umich.edu { return actualTC->getKernelStats(); } 3312654SN/A 3328706Sandreas.hansson@arm.com PortProxy* getPhysProxy() { return actualTC->getPhysProxy(); } 3332521SN/A 3348706Sandreas.hansson@arm.com FSTranslatingPortProxy* getVirtProxy() { return actualTC->getVirtProxy(); } 3353673Srdreslin@umich.edu 3368706Sandreas.hansson@arm.com void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); } 3372SN/A#else 3388706Sandreas.hansson@arm.com SETranslatingPortProxy* getMemProxy() { return actualTC->getMemProxy(); } 3392518SN/A 3402680Sktlim@umich.edu Process *getProcessPtr() { return actualTC->getProcessPtr(); } 3412SN/A#endif 3422SN/A 3432680Sktlim@umich.edu Status status() const { return actualTC->status(); } 344595SN/A 3452680Sktlim@umich.edu void setStatus(Status new_status) { actualTC->setStatus(new_status); } 3462SN/A 3472190SN/A /// Set the status to Active. Optional delay indicates number of 3482190SN/A /// cycles to wait before beginning execution. 3492680Sktlim@umich.edu void activate(int delay = 1) { actualTC->activate(delay); } 3502SN/A 3512190SN/A /// Set the status to Suspended. 3525250Sksewell@umich.edu void suspend(int delay = 0) { actualTC->suspend(); } 3532SN/A 3542190SN/A /// Set the status to Halted. 3555250Sksewell@umich.edu void halt(int delay = 0) { actualTC->halt(); } 356217SN/A 3571858SN/A#if FULL_SYSTEM 3582680Sktlim@umich.edu void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 3592190SN/A#endif 3602190SN/A 3612680Sktlim@umich.edu void takeOverFrom(ThreadContext *oldContext) 3622680Sktlim@umich.edu { actualTC->takeOverFrom(oldContext); } 3632190SN/A 3642680Sktlim@umich.edu void regStats(const std::string &name) { actualTC->regStats(name); } 3652190SN/A 3662680Sktlim@umich.edu void serialize(std::ostream &os) { actualTC->serialize(os); } 3672190SN/A void unserialize(Checkpoint *cp, const std::string §ion) 3682680Sktlim@umich.edu { actualTC->unserialize(cp, section); } 3692190SN/A 3702235SN/A#if FULL_SYSTEM 3712680Sktlim@umich.edu EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 3722235SN/A 3732680Sktlim@umich.edu Tick readLastActivate() { return actualTC->readLastActivate(); } 3742680Sktlim@umich.edu Tick readLastSuspend() { return actualTC->readLastSuspend(); } 3752254SN/A 3762680Sktlim@umich.edu void profileClear() { return actualTC->profileClear(); } 3772680Sktlim@umich.edu void profileSample() { return actualTC->profileSample(); } 3782235SN/A#endif 3792SN/A 3802190SN/A // @todo: Do I need this? 3812680Sktlim@umich.edu void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 3822SN/A 3832680Sktlim@umich.edu void clearArchRegs() { actualTC->clearArchRegs(); } 384716SN/A 3852SN/A // 3862SN/A // New accessors for new decoder. 3872SN/A // 3882SN/A uint64_t readIntReg(int reg_idx) 3892680Sktlim@umich.edu { return actualTC->readIntReg(reg_idx); } 3902SN/A 3912455SN/A FloatReg readFloatReg(int reg_idx) 3922680Sktlim@umich.edu { return actualTC->readFloatReg(reg_idx); } 3932SN/A 3942455SN/A FloatRegBits readFloatRegBits(int reg_idx) 3952680Sktlim@umich.edu { return actualTC->readFloatRegBits(reg_idx); } 3962SN/A 3972SN/A void setIntReg(int reg_idx, uint64_t val) 3982680Sktlim@umich.edu { actualTC->setIntReg(reg_idx, val); } 3992SN/A 4002455SN/A void setFloatReg(int reg_idx, FloatReg val) 4012680Sktlim@umich.edu { actualTC->setFloatReg(reg_idx, val); } 4022SN/A 4032455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 4042680Sktlim@umich.edu { actualTC->setFloatRegBits(reg_idx, val); } 4052SN/A 4067720Sgblack@eecs.umich.edu TheISA::PCState pcState() { return actualTC->pcState(); } 4072SN/A 4087720Sgblack@eecs.umich.edu void pcState(const TheISA::PCState &val) { actualTC->pcState(val); } 4092206SN/A 4108733Sgeoffrey.blake@arm.com#if USE_CHECKER 4118733Sgeoffrey.blake@arm.com void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); } 4128733Sgeoffrey.blake@arm.com#endif 4138733Sgeoffrey.blake@arm.com 4147720Sgblack@eecs.umich.edu Addr instAddr() { return actualTC->instAddr(); } 4157720Sgblack@eecs.umich.edu Addr nextInstAddr() { return actualTC->nextInstAddr(); } 4167720Sgblack@eecs.umich.edu MicroPC microPC() { return actualTC->microPC(); } 4175260Sksewell@umich.edu 4187597Sminkyu.jeong@arm.com bool readPredicate() { return actualTC->readPredicate(); } 4197597Sminkyu.jeong@arm.com 4207597Sminkyu.jeong@arm.com void setPredicate(bool val) 4217597Sminkyu.jeong@arm.com { actualTC->setPredicate(val); } 4227597Sminkyu.jeong@arm.com 4234172Ssaidi@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg) 4244172Ssaidi@eecs.umich.edu { return actualTC->readMiscRegNoEffect(misc_reg); } 4254172Ssaidi@eecs.umich.edu 4262159SN/A MiscReg readMiscReg(int misc_reg) 4272680Sktlim@umich.edu { return actualTC->readMiscReg(misc_reg); } 4282SN/A 4294172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 4304172Ssaidi@eecs.umich.edu { return actualTC->setMiscRegNoEffect(misc_reg, val); } 4312SN/A 4323468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 4332680Sktlim@umich.edu { return actualTC->setMiscReg(misc_reg, val); } 4342SN/A 4356313Sgblack@eecs.umich.edu int flattenIntIndex(int reg) 4366313Sgblack@eecs.umich.edu { return actualTC->flattenIntIndex(reg); } 4376313Sgblack@eecs.umich.edu 4386313Sgblack@eecs.umich.edu int flattenFloatIndex(int reg) 4396313Sgblack@eecs.umich.edu { return actualTC->flattenFloatIndex(reg); } 4406313Sgblack@eecs.umich.edu 4412190SN/A unsigned readStCondFailures() 4422680Sktlim@umich.edu { return actualTC->readStCondFailures(); } 4432190SN/A 4442190SN/A void setStCondFailures(unsigned sc_failures) 4452680Sktlim@umich.edu { actualTC->setStCondFailures(sc_failures); } 4462SN/A 4472190SN/A // @todo: Fix this! 4482680Sktlim@umich.edu bool misspeculating() { return actualTC->misspeculating(); } 4492190SN/A 4501858SN/A#if !FULL_SYSTEM 4514111Sgblack@eecs.umich.edu void syscall(int64_t callnum) 4524111Sgblack@eecs.umich.edu { actualTC->syscall(callnum); } 4534111Sgblack@eecs.umich.edu 4542680Sktlim@umich.edu Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 4552SN/A#endif 4562SN/A}; 4572SN/A 4582190SN/A#endif 459