thread_context.hh revision 8229
12SN/A/* 22190SN/A * Copyright (c) 2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Kevin Lim 292SN/A */ 302SN/A 312680Sktlim@umich.edu#ifndef __CPU_THREAD_CONTEXT_HH__ 322680Sktlim@umich.edu#define __CPU_THREAD_CONTEXT_HH__ 332SN/A 348229Snate@binkert.org#include <iostream> 357680Sgblack@eecs.umich.edu#include <string> 367680Sgblack@eecs.umich.edu 376329Sgblack@eecs.umich.edu#include "arch/registers.hh" 383453Sgblack@eecs.umich.edu#include "arch/types.hh" 396216Snate@binkert.org#include "base/types.hh" 401858SN/A#include "config/full_system.hh" 416658Snate@binkert.org#include "config/the_isa.hh" 422SN/A 432190SN/A// @todo: Figure out a more architecture independent way to obtain the ITB and 442190SN/A// DTB pointers. 453453Sgblack@eecs.umich.edunamespace TheISA 463453Sgblack@eecs.umich.edu{ 476022Sgblack@eecs.umich.edu class TLB; 483453Sgblack@eecs.umich.edu} 492190SN/Aclass BaseCPU; 507680Sgblack@eecs.umich.educlass Checkpoint; 512313SN/Aclass EndQuiesceEvent; 522423SN/Aclass TranslatingPort; 532521SN/Aclass FunctionalPort; 542521SN/Aclass VirtualPort; 552190SN/Aclass Process; 562190SN/Aclass System; 573548Sgblack@eecs.umich.edunamespace TheISA { 583548Sgblack@eecs.umich.edu namespace Kernel { 593548Sgblack@eecs.umich.edu class Statistics; 603548Sgblack@eecs.umich.edu }; 612330SN/A}; 622SN/A 632680Sktlim@umich.edu/** 642680Sktlim@umich.edu * ThreadContext is the external interface to all thread state for 652680Sktlim@umich.edu * anything outside of the CPU. It provides all accessor methods to 662680Sktlim@umich.edu * state that might be needed by external objects, ranging from 672680Sktlim@umich.edu * register values to things such as kernel stats. It is an abstract 682680Sktlim@umich.edu * base class; the CPU can create its own ThreadContext by either 692680Sktlim@umich.edu * deriving from it, or using the templated ProxyThreadContext. 702680Sktlim@umich.edu * 712680Sktlim@umich.edu * The ThreadContext is slightly different than the ExecContext. The 722680Sktlim@umich.edu * ThreadContext provides access to an individual thread's state; an 732680Sktlim@umich.edu * ExecContext provides ISA access to the CPU (meaning it is 742682Sktlim@umich.edu * implicitly multithreaded on SMT systems). Additionally the 752680Sktlim@umich.edu * ThreadState is an abstract class that exactly defines the 762680Sktlim@umich.edu * interface; the ExecContext is a more implicit interface that must 772680Sktlim@umich.edu * be implemented so that the ISA can access whatever state it needs. 782680Sktlim@umich.edu */ 792680Sktlim@umich.educlass ThreadContext 802SN/A{ 812107SN/A protected: 822107SN/A typedef TheISA::MachInst MachInst; 832190SN/A typedef TheISA::IntReg IntReg; 842455SN/A typedef TheISA::FloatReg FloatReg; 852455SN/A typedef TheISA::FloatRegBits FloatRegBits; 862159SN/A typedef TheISA::MiscReg MiscReg; 872SN/A public: 886029Ssteve.reinhardt@amd.com 89246SN/A enum Status 90246SN/A { 91246SN/A /// Running. Instructions should be executed only when 92246SN/A /// the context is in this state. 93246SN/A Active, 94246SN/A 95246SN/A /// Temporarily inactive. Entered while waiting for 962190SN/A /// synchronization, etc. 97246SN/A Suspended, 98246SN/A 99246SN/A /// Permanently shut down. Entered when target executes 100246SN/A /// m5exit pseudo-instruction. When all contexts enter 101246SN/A /// this state, the simulation will terminate. 102246SN/A Halted 103246SN/A }; 1042SN/A 1052680Sktlim@umich.edu virtual ~ThreadContext() { }; 1062423SN/A 1072190SN/A virtual BaseCPU *getCpuPtr() = 0; 108180SN/A 1095712Shsul@eecs.umich.edu virtual int cpuId() = 0; 1102190SN/A 1115715Shsul@eecs.umich.edu virtual int threadId() = 0; 1125715Shsul@eecs.umich.edu 1135715Shsul@eecs.umich.edu virtual void setThreadId(int id) = 0; 1145714Shsul@eecs.umich.edu 1155714Shsul@eecs.umich.edu virtual int contextId() = 0; 1165714Shsul@eecs.umich.edu 1175714Shsul@eecs.umich.edu virtual void setContextId(int id) = 0; 1185714Shsul@eecs.umich.edu 1196022Sgblack@eecs.umich.edu virtual TheISA::TLB *getITBPtr() = 0; 1202190SN/A 1216022Sgblack@eecs.umich.edu virtual TheISA::TLB *getDTBPtr() = 0; 1222521SN/A 1234997Sgblack@eecs.umich.edu virtual System *getSystemPtr() = 0; 1244997Sgblack@eecs.umich.edu 1255803Snate@binkert.org#if FULL_SYSTEM 1263548Sgblack@eecs.umich.edu virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 1272654SN/A 1282521SN/A virtual FunctionalPort *getPhysPort() = 0; 1292521SN/A 1305499Ssaidi@eecs.umich.edu virtual VirtualPort *getVirtPort() = 0; 1313673Srdreslin@umich.edu 1325497Ssaidi@eecs.umich.edu virtual void connectMemPorts(ThreadContext *tc) = 0; 1332190SN/A#else 1342518SN/A virtual TranslatingPort *getMemPort() = 0; 1352518SN/A 1362190SN/A virtual Process *getProcessPtr() = 0; 1372190SN/A#endif 1382190SN/A 1392190SN/A virtual Status status() const = 0; 1402159SN/A 1412235SN/A virtual void setStatus(Status new_status) = 0; 1422103SN/A 143393SN/A /// Set the status to Active. Optional delay indicates number of 144393SN/A /// cycles to wait before beginning execution. 1452190SN/A virtual void activate(int delay = 1) = 0; 146393SN/A 147393SN/A /// Set the status to Suspended. 1485250Sksewell@umich.edu virtual void suspend(int delay = 0) = 0; 149393SN/A 150393SN/A /// Set the status to Halted. 1515250Sksewell@umich.edu virtual void halt(int delay = 0) = 0; 1522159SN/A 1532159SN/A#if FULL_SYSTEM 1542190SN/A virtual void dumpFuncProfile() = 0; 1552159SN/A#endif 1562159SN/A 1572680Sktlim@umich.edu virtual void takeOverFrom(ThreadContext *old_context) = 0; 1582159SN/A 1592190SN/A virtual void regStats(const std::string &name) = 0; 1602159SN/A 1612190SN/A virtual void serialize(std::ostream &os) = 0; 1622190SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 1632159SN/A 1642235SN/A#if FULL_SYSTEM 1652313SN/A virtual EndQuiesceEvent *getQuiesceEvent() = 0; 1662235SN/A 1672235SN/A // Not necessarily the best location for these... 1682235SN/A // Having an extra function just to read these is obnoxious 1692235SN/A virtual Tick readLastActivate() = 0; 1702235SN/A virtual Tick readLastSuspend() = 0; 1712254SN/A 1722254SN/A virtual void profileClear() = 0; 1732254SN/A virtual void profileSample() = 0; 1742235SN/A#endif 1752235SN/A 1762680Sktlim@umich.edu virtual void copyArchRegs(ThreadContext *tc) = 0; 1772159SN/A 1782190SN/A virtual void clearArchRegs() = 0; 1792159SN/A 1802159SN/A // 1812159SN/A // New accessors for new decoder. 1822159SN/A // 1832190SN/A virtual uint64_t readIntReg(int reg_idx) = 0; 1842159SN/A 1852455SN/A virtual FloatReg readFloatReg(int reg_idx) = 0; 1862159SN/A 1872455SN/A virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 1882159SN/A 1892190SN/A virtual void setIntReg(int reg_idx, uint64_t val) = 0; 1902159SN/A 1912455SN/A virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 1922159SN/A 1932455SN/A virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 1942455SN/A 1957720Sgblack@eecs.umich.edu virtual TheISA::PCState pcState() = 0; 1962159SN/A 1977720Sgblack@eecs.umich.edu virtual void pcState(const TheISA::PCState &val) = 0; 1982159SN/A 1997720Sgblack@eecs.umich.edu virtual Addr instAddr() = 0; 2002159SN/A 2017720Sgblack@eecs.umich.edu virtual Addr nextInstAddr() = 0; 2022159SN/A 2037720Sgblack@eecs.umich.edu virtual MicroPC microPC() = 0; 2045260Sksewell@umich.edu 2054172Ssaidi@eecs.umich.edu virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; 2064172Ssaidi@eecs.umich.edu 2072190SN/A virtual MiscReg readMiscReg(int misc_reg) = 0; 2082159SN/A 2094172Ssaidi@eecs.umich.edu virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; 2102190SN/A 2113468Sgblack@eecs.umich.edu virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 2122190SN/A 2136313Sgblack@eecs.umich.edu virtual int flattenIntIndex(int reg) = 0; 2146313Sgblack@eecs.umich.edu virtual int flattenFloatIndex(int reg) = 0; 2156313Sgblack@eecs.umich.edu 2166221Snate@binkert.org virtual uint64_t 2176221Snate@binkert.org readRegOtherThread(int misc_reg, ThreadID tid) 2186221Snate@binkert.org { 2196221Snate@binkert.org return 0; 2206221Snate@binkert.org } 2214661Sksewell@umich.edu 2226221Snate@binkert.org virtual void 2236221Snate@binkert.org setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid) 2246221Snate@binkert.org { 2256221Snate@binkert.org } 2264661Sksewell@umich.edu 2272235SN/A // Also not necessarily the best location for these two. Hopefully will go 2282235SN/A // away once we decide upon where st cond failures goes. 2292190SN/A virtual unsigned readStCondFailures() = 0; 2302190SN/A 2312190SN/A virtual void setStCondFailures(unsigned sc_failures) = 0; 2322159SN/A 2332235SN/A // Only really makes sense for old CPU model. Still could be useful though. 2342190SN/A virtual bool misspeculating() = 0; 2352190SN/A 2362159SN/A#if !FULL_SYSTEM 2372235SN/A // Same with st cond failures. 2382190SN/A virtual Counter readFuncExeInst() = 0; 2392834Sksewell@umich.edu 2404111Sgblack@eecs.umich.edu virtual void syscall(int64_t callnum) = 0; 2414111Sgblack@eecs.umich.edu 2422834Sksewell@umich.edu // This function exits the thread context in the CPU and returns 2432834Sksewell@umich.edu // 1 if the CPU has no more active threads (meaning it's OK to exit); 2442834Sksewell@umich.edu // Used in syscall-emulation mode when a thread calls the exit syscall. 2452834Sksewell@umich.edu virtual int exit() { return 1; }; 2462159SN/A#endif 2472525SN/A 2485217Ssaidi@eecs.umich.edu /** function to compare two thread contexts (for debugging) */ 2495217Ssaidi@eecs.umich.edu static void compare(ThreadContext *one, ThreadContext *two); 2502159SN/A}; 2512159SN/A 2522682Sktlim@umich.edu/** 2532682Sktlim@umich.edu * ProxyThreadContext class that provides a way to implement a 2542682Sktlim@umich.edu * ThreadContext without having to derive from it. ThreadContext is an 2552682Sktlim@umich.edu * abstract class, so anything that derives from it and uses its 2562682Sktlim@umich.edu * interface will pay the overhead of virtual function calls. This 2572682Sktlim@umich.edu * class is created to enable a user-defined Thread object to be used 2582682Sktlim@umich.edu * wherever ThreadContexts are used, without paying the overhead of 2592682Sktlim@umich.edu * virtual function calls when it is used by itself. See 2602682Sktlim@umich.edu * simple_thread.hh for an example of this. 2612682Sktlim@umich.edu */ 2622680Sktlim@umich.edutemplate <class TC> 2632680Sktlim@umich.educlass ProxyThreadContext : public ThreadContext 2642190SN/A{ 2652190SN/A public: 2662680Sktlim@umich.edu ProxyThreadContext(TC *actual_tc) 2672680Sktlim@umich.edu { actualTC = actual_tc; } 2682159SN/A 2692190SN/A private: 2702680Sktlim@umich.edu TC *actualTC; 2712SN/A 2722SN/A public: 2732SN/A 2742680Sktlim@umich.edu BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 2752SN/A 2765712Shsul@eecs.umich.edu int cpuId() { return actualTC->cpuId(); } 2772SN/A 2785715Shsul@eecs.umich.edu int threadId() { return actualTC->threadId(); } 2795715Shsul@eecs.umich.edu 2805715Shsul@eecs.umich.edu void setThreadId(int id) { return actualTC->setThreadId(id); } 2815714Shsul@eecs.umich.edu 2825714Shsul@eecs.umich.edu int contextId() { return actualTC->contextId(); } 2835714Shsul@eecs.umich.edu 2845714Shsul@eecs.umich.edu void setContextId(int id) { actualTC->setContextId(id); } 2855714Shsul@eecs.umich.edu 2866022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 2871917SN/A 2886022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 2892521SN/A 2904997Sgblack@eecs.umich.edu System *getSystemPtr() { return actualTC->getSystemPtr(); } 2914997Sgblack@eecs.umich.edu 2925803Snate@binkert.org#if FULL_SYSTEM 2933548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *getKernelStats() 2943548Sgblack@eecs.umich.edu { return actualTC->getKernelStats(); } 2952654SN/A 2962680Sktlim@umich.edu FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); } 2972521SN/A 2985499Ssaidi@eecs.umich.edu VirtualPort *getVirtPort() { return actualTC->getVirtPort(); } 2993673Srdreslin@umich.edu 3005497Ssaidi@eecs.umich.edu void connectMemPorts(ThreadContext *tc) { actualTC->connectMemPorts(tc); } 3012SN/A#else 3022680Sktlim@umich.edu TranslatingPort *getMemPort() { return actualTC->getMemPort(); } 3032518SN/A 3042680Sktlim@umich.edu Process *getProcessPtr() { return actualTC->getProcessPtr(); } 3052SN/A#endif 3062SN/A 3072680Sktlim@umich.edu Status status() const { return actualTC->status(); } 308595SN/A 3092680Sktlim@umich.edu void setStatus(Status new_status) { actualTC->setStatus(new_status); } 3102SN/A 3112190SN/A /// Set the status to Active. Optional delay indicates number of 3122190SN/A /// cycles to wait before beginning execution. 3132680Sktlim@umich.edu void activate(int delay = 1) { actualTC->activate(delay); } 3142SN/A 3152190SN/A /// Set the status to Suspended. 3165250Sksewell@umich.edu void suspend(int delay = 0) { actualTC->suspend(); } 3172SN/A 3182190SN/A /// Set the status to Halted. 3195250Sksewell@umich.edu void halt(int delay = 0) { actualTC->halt(); } 320217SN/A 3211858SN/A#if FULL_SYSTEM 3222680Sktlim@umich.edu void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 3232190SN/A#endif 3242190SN/A 3252680Sktlim@umich.edu void takeOverFrom(ThreadContext *oldContext) 3262680Sktlim@umich.edu { actualTC->takeOverFrom(oldContext); } 3272190SN/A 3282680Sktlim@umich.edu void regStats(const std::string &name) { actualTC->regStats(name); } 3292190SN/A 3302680Sktlim@umich.edu void serialize(std::ostream &os) { actualTC->serialize(os); } 3312190SN/A void unserialize(Checkpoint *cp, const std::string §ion) 3322680Sktlim@umich.edu { actualTC->unserialize(cp, section); } 3332190SN/A 3342235SN/A#if FULL_SYSTEM 3352680Sktlim@umich.edu EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 3362235SN/A 3372680Sktlim@umich.edu Tick readLastActivate() { return actualTC->readLastActivate(); } 3382680Sktlim@umich.edu Tick readLastSuspend() { return actualTC->readLastSuspend(); } 3392254SN/A 3402680Sktlim@umich.edu void profileClear() { return actualTC->profileClear(); } 3412680Sktlim@umich.edu void profileSample() { return actualTC->profileSample(); } 3422235SN/A#endif 3432SN/A 3442190SN/A // @todo: Do I need this? 3452680Sktlim@umich.edu void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 3462SN/A 3472680Sktlim@umich.edu void clearArchRegs() { actualTC->clearArchRegs(); } 348716SN/A 3492SN/A // 3502SN/A // New accessors for new decoder. 3512SN/A // 3522SN/A uint64_t readIntReg(int reg_idx) 3532680Sktlim@umich.edu { return actualTC->readIntReg(reg_idx); } 3542SN/A 3552455SN/A FloatReg readFloatReg(int reg_idx) 3562680Sktlim@umich.edu { return actualTC->readFloatReg(reg_idx); } 3572SN/A 3582455SN/A FloatRegBits readFloatRegBits(int reg_idx) 3592680Sktlim@umich.edu { return actualTC->readFloatRegBits(reg_idx); } 3602SN/A 3612SN/A void setIntReg(int reg_idx, uint64_t val) 3622680Sktlim@umich.edu { actualTC->setIntReg(reg_idx, val); } 3632SN/A 3642455SN/A void setFloatReg(int reg_idx, FloatReg val) 3652680Sktlim@umich.edu { actualTC->setFloatReg(reg_idx, val); } 3662SN/A 3672455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 3682680Sktlim@umich.edu { actualTC->setFloatRegBits(reg_idx, val); } 3692SN/A 3707720Sgblack@eecs.umich.edu TheISA::PCState pcState() { return actualTC->pcState(); } 3712SN/A 3727720Sgblack@eecs.umich.edu void pcState(const TheISA::PCState &val) { actualTC->pcState(val); } 3732206SN/A 3747720Sgblack@eecs.umich.edu Addr instAddr() { return actualTC->instAddr(); } 3757720Sgblack@eecs.umich.edu Addr nextInstAddr() { return actualTC->nextInstAddr(); } 3767720Sgblack@eecs.umich.edu MicroPC microPC() { return actualTC->microPC(); } 3775260Sksewell@umich.edu 3787597Sminkyu.jeong@arm.com bool readPredicate() { return actualTC->readPredicate(); } 3797597Sminkyu.jeong@arm.com 3807597Sminkyu.jeong@arm.com void setPredicate(bool val) 3817597Sminkyu.jeong@arm.com { actualTC->setPredicate(val); } 3827597Sminkyu.jeong@arm.com 3834172Ssaidi@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg) 3844172Ssaidi@eecs.umich.edu { return actualTC->readMiscRegNoEffect(misc_reg); } 3854172Ssaidi@eecs.umich.edu 3862159SN/A MiscReg readMiscReg(int misc_reg) 3872680Sktlim@umich.edu { return actualTC->readMiscReg(misc_reg); } 3882SN/A 3894172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 3904172Ssaidi@eecs.umich.edu { return actualTC->setMiscRegNoEffect(misc_reg, val); } 3912SN/A 3923468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 3932680Sktlim@umich.edu { return actualTC->setMiscReg(misc_reg, val); } 3942SN/A 3956313Sgblack@eecs.umich.edu int flattenIntIndex(int reg) 3966313Sgblack@eecs.umich.edu { return actualTC->flattenIntIndex(reg); } 3976313Sgblack@eecs.umich.edu 3986313Sgblack@eecs.umich.edu int flattenFloatIndex(int reg) 3996313Sgblack@eecs.umich.edu { return actualTC->flattenFloatIndex(reg); } 4006313Sgblack@eecs.umich.edu 4012190SN/A unsigned readStCondFailures() 4022680Sktlim@umich.edu { return actualTC->readStCondFailures(); } 4032190SN/A 4042190SN/A void setStCondFailures(unsigned sc_failures) 4052680Sktlim@umich.edu { actualTC->setStCondFailures(sc_failures); } 4062SN/A 4072190SN/A // @todo: Fix this! 4082680Sktlim@umich.edu bool misspeculating() { return actualTC->misspeculating(); } 4092190SN/A 4101858SN/A#if !FULL_SYSTEM 4114111Sgblack@eecs.umich.edu void syscall(int64_t callnum) 4124111Sgblack@eecs.umich.edu { actualTC->syscall(callnum); } 4134111Sgblack@eecs.umich.edu 4142680Sktlim@umich.edu Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 4152SN/A#endif 4162SN/A}; 4172SN/A 4182190SN/A#endif 419