thread_context.hh revision 6221
12SN/A/* 22190SN/A * Copyright (c) 2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Kevin Lim 292SN/A */ 302SN/A 312680Sktlim@umich.edu#ifndef __CPU_THREAD_CONTEXT_HH__ 322680Sktlim@umich.edu#define __CPU_THREAD_CONTEXT_HH__ 332SN/A 342972Sgblack@eecs.umich.edu#include "arch/regfile.hh" 353453Sgblack@eecs.umich.edu#include "arch/types.hh" 366216Snate@binkert.org#include "base/types.hh" 371858SN/A#include "config/full_system.hh" 382423SN/A#include "mem/request.hh" 396216Snate@binkert.org#include "sim/byteswap.hh" 402190SN/A#include "sim/faults.hh" 41217SN/A#include "sim/serialize.hh" 422SN/A 432190SN/A// @todo: Figure out a more architecture independent way to obtain the ITB and 442190SN/A// DTB pointers. 453453Sgblack@eecs.umich.edunamespace TheISA 463453Sgblack@eecs.umich.edu{ 476022Sgblack@eecs.umich.edu class TLB; 483453Sgblack@eecs.umich.edu} 492190SN/Aclass BaseCPU; 502313SN/Aclass EndQuiesceEvent; 512235SN/Aclass Event; 522423SN/Aclass TranslatingPort; 532521SN/Aclass FunctionalPort; 542521SN/Aclass VirtualPort; 552190SN/Aclass Process; 562190SN/Aclass System; 573548Sgblack@eecs.umich.edunamespace TheISA { 583548Sgblack@eecs.umich.edu namespace Kernel { 593548Sgblack@eecs.umich.edu class Statistics; 603548Sgblack@eecs.umich.edu }; 612330SN/A}; 622SN/A 632680Sktlim@umich.edu/** 642680Sktlim@umich.edu * ThreadContext is the external interface to all thread state for 652680Sktlim@umich.edu * anything outside of the CPU. It provides all accessor methods to 662680Sktlim@umich.edu * state that might be needed by external objects, ranging from 672680Sktlim@umich.edu * register values to things such as kernel stats. It is an abstract 682680Sktlim@umich.edu * base class; the CPU can create its own ThreadContext by either 692680Sktlim@umich.edu * deriving from it, or using the templated ProxyThreadContext. 702680Sktlim@umich.edu * 712680Sktlim@umich.edu * The ThreadContext is slightly different than the ExecContext. The 722680Sktlim@umich.edu * ThreadContext provides access to an individual thread's state; an 732680Sktlim@umich.edu * ExecContext provides ISA access to the CPU (meaning it is 742682Sktlim@umich.edu * implicitly multithreaded on SMT systems). Additionally the 752680Sktlim@umich.edu * ThreadState is an abstract class that exactly defines the 762680Sktlim@umich.edu * interface; the ExecContext is a more implicit interface that must 772680Sktlim@umich.edu * be implemented so that the ISA can access whatever state it needs. 782680Sktlim@umich.edu */ 792680Sktlim@umich.educlass ThreadContext 802SN/A{ 812107SN/A protected: 822107SN/A typedef TheISA::RegFile RegFile; 832107SN/A typedef TheISA::MachInst MachInst; 842190SN/A typedef TheISA::IntReg IntReg; 852455SN/A typedef TheISA::FloatReg FloatReg; 862455SN/A typedef TheISA::FloatRegBits FloatRegBits; 872107SN/A typedef TheISA::MiscRegFile MiscRegFile; 882159SN/A typedef TheISA::MiscReg MiscReg; 892SN/A public: 906029Ssteve.reinhardt@amd.com 91246SN/A enum Status 92246SN/A { 93246SN/A /// Running. Instructions should be executed only when 94246SN/A /// the context is in this state. 95246SN/A Active, 96246SN/A 97246SN/A /// Temporarily inactive. Entered while waiting for 982190SN/A /// synchronization, etc. 99246SN/A Suspended, 100246SN/A 101246SN/A /// Permanently shut down. Entered when target executes 102246SN/A /// m5exit pseudo-instruction. When all contexts enter 103246SN/A /// this state, the simulation will terminate. 104246SN/A Halted 105246SN/A }; 1062SN/A 1072680Sktlim@umich.edu virtual ~ThreadContext() { }; 1082423SN/A 1092190SN/A virtual BaseCPU *getCpuPtr() = 0; 110180SN/A 1115712Shsul@eecs.umich.edu virtual int cpuId() = 0; 1122190SN/A 1135715Shsul@eecs.umich.edu virtual int threadId() = 0; 1145715Shsul@eecs.umich.edu 1155715Shsul@eecs.umich.edu virtual void setThreadId(int id) = 0; 1165714Shsul@eecs.umich.edu 1175714Shsul@eecs.umich.edu virtual int contextId() = 0; 1185714Shsul@eecs.umich.edu 1195714Shsul@eecs.umich.edu virtual void setContextId(int id) = 0; 1205714Shsul@eecs.umich.edu 1216022Sgblack@eecs.umich.edu virtual TheISA::TLB *getITBPtr() = 0; 1222190SN/A 1236022Sgblack@eecs.umich.edu virtual TheISA::TLB *getDTBPtr() = 0; 1242521SN/A 1254997Sgblack@eecs.umich.edu virtual System *getSystemPtr() = 0; 1264997Sgblack@eecs.umich.edu 1275803Snate@binkert.org#if FULL_SYSTEM 1283548Sgblack@eecs.umich.edu virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 1292654SN/A 1302521SN/A virtual FunctionalPort *getPhysPort() = 0; 1312521SN/A 1325499Ssaidi@eecs.umich.edu virtual VirtualPort *getVirtPort() = 0; 1333673Srdreslin@umich.edu 1345497Ssaidi@eecs.umich.edu virtual void connectMemPorts(ThreadContext *tc) = 0; 1352190SN/A#else 1362518SN/A virtual TranslatingPort *getMemPort() = 0; 1372518SN/A 1382190SN/A virtual Process *getProcessPtr() = 0; 1392190SN/A#endif 1402190SN/A 1412190SN/A virtual Status status() const = 0; 1422159SN/A 1432235SN/A virtual void setStatus(Status new_status) = 0; 1442103SN/A 145393SN/A /// Set the status to Active. Optional delay indicates number of 146393SN/A /// cycles to wait before beginning execution. 1472190SN/A virtual void activate(int delay = 1) = 0; 148393SN/A 149393SN/A /// Set the status to Suspended. 1505250Sksewell@umich.edu virtual void suspend(int delay = 0) = 0; 151393SN/A 152393SN/A /// Set the status to Halted. 1535250Sksewell@umich.edu virtual void halt(int delay = 0) = 0; 1542159SN/A 1552159SN/A#if FULL_SYSTEM 1562190SN/A virtual void dumpFuncProfile() = 0; 1572159SN/A#endif 1582159SN/A 1592680Sktlim@umich.edu virtual void takeOverFrom(ThreadContext *old_context) = 0; 1602159SN/A 1612190SN/A virtual void regStats(const std::string &name) = 0; 1622159SN/A 1632190SN/A virtual void serialize(std::ostream &os) = 0; 1642190SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 1652159SN/A 1662235SN/A#if FULL_SYSTEM 1672313SN/A virtual EndQuiesceEvent *getQuiesceEvent() = 0; 1682235SN/A 1692235SN/A // Not necessarily the best location for these... 1702235SN/A // Having an extra function just to read these is obnoxious 1712235SN/A virtual Tick readLastActivate() = 0; 1722235SN/A virtual Tick readLastSuspend() = 0; 1732254SN/A 1742254SN/A virtual void profileClear() = 0; 1752254SN/A virtual void profileSample() = 0; 1762235SN/A#endif 1772235SN/A 1782235SN/A // Also somewhat obnoxious. Really only used for the TLB fault. 1792254SN/A // However, may be quite useful in SPARC. 1802190SN/A virtual TheISA::MachInst getInst() = 0; 1812159SN/A 1822680Sktlim@umich.edu virtual void copyArchRegs(ThreadContext *tc) = 0; 1832159SN/A 1842190SN/A virtual void clearArchRegs() = 0; 1852159SN/A 1862159SN/A // 1872159SN/A // New accessors for new decoder. 1882159SN/A // 1892190SN/A virtual uint64_t readIntReg(int reg_idx) = 0; 1902159SN/A 1912455SN/A virtual FloatReg readFloatReg(int reg_idx, int width) = 0; 1922159SN/A 1932455SN/A virtual FloatReg readFloatReg(int reg_idx) = 0; 1942159SN/A 1952455SN/A virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0; 1962455SN/A 1972455SN/A virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 1982159SN/A 1992190SN/A virtual void setIntReg(int reg_idx, uint64_t val) = 0; 2002159SN/A 2012455SN/A virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0; 2022159SN/A 2032455SN/A virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 2042159SN/A 2052455SN/A virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 2062455SN/A 2072455SN/A virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0; 2082159SN/A 2092190SN/A virtual uint64_t readPC() = 0; 2102159SN/A 2112190SN/A virtual void setPC(uint64_t val) = 0; 2122159SN/A 2132190SN/A virtual uint64_t readNextPC() = 0; 2142159SN/A 2152190SN/A virtual void setNextPC(uint64_t val) = 0; 2162159SN/A 2172447SN/A virtual uint64_t readNextNPC() = 0; 2182447SN/A 2192447SN/A virtual void setNextNPC(uint64_t val) = 0; 2202447SN/A 2215260Sksewell@umich.edu virtual uint64_t readMicroPC() = 0; 2225260Sksewell@umich.edu 2235260Sksewell@umich.edu virtual void setMicroPC(uint64_t val) = 0; 2245260Sksewell@umich.edu 2255260Sksewell@umich.edu virtual uint64_t readNextMicroPC() = 0; 2265260Sksewell@umich.edu 2275260Sksewell@umich.edu virtual void setNextMicroPC(uint64_t val) = 0; 2285260Sksewell@umich.edu 2294172Ssaidi@eecs.umich.edu virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; 2304172Ssaidi@eecs.umich.edu 2312190SN/A virtual MiscReg readMiscReg(int misc_reg) = 0; 2322159SN/A 2334172Ssaidi@eecs.umich.edu virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; 2342190SN/A 2353468Sgblack@eecs.umich.edu virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 2362190SN/A 2376221Snate@binkert.org virtual uint64_t 2386221Snate@binkert.org readRegOtherThread(int misc_reg, ThreadID tid) 2396221Snate@binkert.org { 2406221Snate@binkert.org return 0; 2416221Snate@binkert.org } 2424661Sksewell@umich.edu 2436221Snate@binkert.org virtual void 2446221Snate@binkert.org setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid) 2456221Snate@binkert.org { 2466221Snate@binkert.org } 2474661Sksewell@umich.edu 2482235SN/A // Also not necessarily the best location for these two. Hopefully will go 2492235SN/A // away once we decide upon where st cond failures goes. 2502190SN/A virtual unsigned readStCondFailures() = 0; 2512190SN/A 2522190SN/A virtual void setStCondFailures(unsigned sc_failures) = 0; 2532159SN/A 2542235SN/A // Only really makes sense for old CPU model. Still could be useful though. 2552190SN/A virtual bool misspeculating() = 0; 2562190SN/A 2572159SN/A#if !FULL_SYSTEM 2582235SN/A // Same with st cond failures. 2592190SN/A virtual Counter readFuncExeInst() = 0; 2602834Sksewell@umich.edu 2614111Sgblack@eecs.umich.edu virtual void syscall(int64_t callnum) = 0; 2624111Sgblack@eecs.umich.edu 2632834Sksewell@umich.edu // This function exits the thread context in the CPU and returns 2642834Sksewell@umich.edu // 1 if the CPU has no more active threads (meaning it's OK to exit); 2652834Sksewell@umich.edu // Used in syscall-emulation mode when a thread calls the exit syscall. 2662834Sksewell@umich.edu virtual int exit() { return 1; }; 2672159SN/A#endif 2682525SN/A 2695217Ssaidi@eecs.umich.edu /** function to compare two thread contexts (for debugging) */ 2705217Ssaidi@eecs.umich.edu static void compare(ThreadContext *one, ThreadContext *two); 2712159SN/A}; 2722159SN/A 2732682Sktlim@umich.edu/** 2742682Sktlim@umich.edu * ProxyThreadContext class that provides a way to implement a 2752682Sktlim@umich.edu * ThreadContext without having to derive from it. ThreadContext is an 2762682Sktlim@umich.edu * abstract class, so anything that derives from it and uses its 2772682Sktlim@umich.edu * interface will pay the overhead of virtual function calls. This 2782682Sktlim@umich.edu * class is created to enable a user-defined Thread object to be used 2792682Sktlim@umich.edu * wherever ThreadContexts are used, without paying the overhead of 2802682Sktlim@umich.edu * virtual function calls when it is used by itself. See 2812682Sktlim@umich.edu * simple_thread.hh for an example of this. 2822682Sktlim@umich.edu */ 2832680Sktlim@umich.edutemplate <class TC> 2842680Sktlim@umich.educlass ProxyThreadContext : public ThreadContext 2852190SN/A{ 2862190SN/A public: 2872680Sktlim@umich.edu ProxyThreadContext(TC *actual_tc) 2882680Sktlim@umich.edu { actualTC = actual_tc; } 2892159SN/A 2902190SN/A private: 2912680Sktlim@umich.edu TC *actualTC; 2922SN/A 2932SN/A public: 2942SN/A 2952680Sktlim@umich.edu BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 2962SN/A 2975712Shsul@eecs.umich.edu int cpuId() { return actualTC->cpuId(); } 2982SN/A 2995715Shsul@eecs.umich.edu int threadId() { return actualTC->threadId(); } 3005715Shsul@eecs.umich.edu 3015715Shsul@eecs.umich.edu void setThreadId(int id) { return actualTC->setThreadId(id); } 3025714Shsul@eecs.umich.edu 3035714Shsul@eecs.umich.edu int contextId() { return actualTC->contextId(); } 3045714Shsul@eecs.umich.edu 3055714Shsul@eecs.umich.edu void setContextId(int id) { actualTC->setContextId(id); } 3065714Shsul@eecs.umich.edu 3076022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 3081917SN/A 3096022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 3102521SN/A 3114997Sgblack@eecs.umich.edu System *getSystemPtr() { return actualTC->getSystemPtr(); } 3124997Sgblack@eecs.umich.edu 3135803Snate@binkert.org#if FULL_SYSTEM 3143548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *getKernelStats() 3153548Sgblack@eecs.umich.edu { return actualTC->getKernelStats(); } 3162654SN/A 3172680Sktlim@umich.edu FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); } 3182521SN/A 3195499Ssaidi@eecs.umich.edu VirtualPort *getVirtPort() { return actualTC->getVirtPort(); } 3203673Srdreslin@umich.edu 3215497Ssaidi@eecs.umich.edu void connectMemPorts(ThreadContext *tc) { actualTC->connectMemPorts(tc); } 3222SN/A#else 3232680Sktlim@umich.edu TranslatingPort *getMemPort() { return actualTC->getMemPort(); } 3242518SN/A 3252680Sktlim@umich.edu Process *getProcessPtr() { return actualTC->getProcessPtr(); } 3262SN/A#endif 3272SN/A 3282680Sktlim@umich.edu Status status() const { return actualTC->status(); } 329595SN/A 3302680Sktlim@umich.edu void setStatus(Status new_status) { actualTC->setStatus(new_status); } 3312SN/A 3322190SN/A /// Set the status to Active. Optional delay indicates number of 3332190SN/A /// cycles to wait before beginning execution. 3342680Sktlim@umich.edu void activate(int delay = 1) { actualTC->activate(delay); } 3352SN/A 3362190SN/A /// Set the status to Suspended. 3375250Sksewell@umich.edu void suspend(int delay = 0) { actualTC->suspend(); } 3382SN/A 3392190SN/A /// Set the status to Halted. 3405250Sksewell@umich.edu void halt(int delay = 0) { actualTC->halt(); } 341217SN/A 3421858SN/A#if FULL_SYSTEM 3432680Sktlim@umich.edu void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 3442190SN/A#endif 3452190SN/A 3462680Sktlim@umich.edu void takeOverFrom(ThreadContext *oldContext) 3472680Sktlim@umich.edu { actualTC->takeOverFrom(oldContext); } 3482190SN/A 3492680Sktlim@umich.edu void regStats(const std::string &name) { actualTC->regStats(name); } 3502190SN/A 3512680Sktlim@umich.edu void serialize(std::ostream &os) { actualTC->serialize(os); } 3522190SN/A void unserialize(Checkpoint *cp, const std::string §ion) 3532680Sktlim@umich.edu { actualTC->unserialize(cp, section); } 3542190SN/A 3552235SN/A#if FULL_SYSTEM 3562680Sktlim@umich.edu EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 3572235SN/A 3582680Sktlim@umich.edu Tick readLastActivate() { return actualTC->readLastActivate(); } 3592680Sktlim@umich.edu Tick readLastSuspend() { return actualTC->readLastSuspend(); } 3602254SN/A 3612680Sktlim@umich.edu void profileClear() { return actualTC->profileClear(); } 3622680Sktlim@umich.edu void profileSample() { return actualTC->profileSample(); } 3632235SN/A#endif 3642190SN/A // @todo: Do I need this? 3652680Sktlim@umich.edu MachInst getInst() { return actualTC->getInst(); } 3662SN/A 3672190SN/A // @todo: Do I need this? 3682680Sktlim@umich.edu void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 3692SN/A 3702680Sktlim@umich.edu void clearArchRegs() { actualTC->clearArchRegs(); } 371716SN/A 3722SN/A // 3732SN/A // New accessors for new decoder. 3742SN/A // 3752SN/A uint64_t readIntReg(int reg_idx) 3762680Sktlim@umich.edu { return actualTC->readIntReg(reg_idx); } 3772SN/A 3782455SN/A FloatReg readFloatReg(int reg_idx, int width) 3792680Sktlim@umich.edu { return actualTC->readFloatReg(reg_idx, width); } 3802SN/A 3812455SN/A FloatReg readFloatReg(int reg_idx) 3822680Sktlim@umich.edu { return actualTC->readFloatReg(reg_idx); } 3832SN/A 3842455SN/A FloatRegBits readFloatRegBits(int reg_idx, int width) 3852680Sktlim@umich.edu { return actualTC->readFloatRegBits(reg_idx, width); } 3862455SN/A 3872455SN/A FloatRegBits readFloatRegBits(int reg_idx) 3882680Sktlim@umich.edu { return actualTC->readFloatRegBits(reg_idx); } 3892SN/A 3902SN/A void setIntReg(int reg_idx, uint64_t val) 3912680Sktlim@umich.edu { actualTC->setIntReg(reg_idx, val); } 3922SN/A 3932455SN/A void setFloatReg(int reg_idx, FloatReg val, int width) 3942680Sktlim@umich.edu { actualTC->setFloatReg(reg_idx, val, width); } 3952SN/A 3962455SN/A void setFloatReg(int reg_idx, FloatReg val) 3972680Sktlim@umich.edu { actualTC->setFloatReg(reg_idx, val); } 3982SN/A 3992455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 4002680Sktlim@umich.edu { actualTC->setFloatRegBits(reg_idx, val, width); } 4012455SN/A 4022455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 4032680Sktlim@umich.edu { actualTC->setFloatRegBits(reg_idx, val); } 4042SN/A 4052680Sktlim@umich.edu uint64_t readPC() { return actualTC->readPC(); } 4062SN/A 4072680Sktlim@umich.edu void setPC(uint64_t val) { actualTC->setPC(val); } 4082206SN/A 4092680Sktlim@umich.edu uint64_t readNextPC() { return actualTC->readNextPC(); } 4102252SN/A 4112680Sktlim@umich.edu void setNextPC(uint64_t val) { actualTC->setNextPC(val); } 4122SN/A 4132680Sktlim@umich.edu uint64_t readNextNPC() { return actualTC->readNextNPC(); } 4142447SN/A 4152680Sktlim@umich.edu void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); } 4162447SN/A 4175260Sksewell@umich.edu uint64_t readMicroPC() { return actualTC->readMicroPC(); } 4185260Sksewell@umich.edu 4195260Sksewell@umich.edu void setMicroPC(uint64_t val) { actualTC->setMicroPC(val); } 4205260Sksewell@umich.edu 4215260Sksewell@umich.edu uint64_t readNextMicroPC() { return actualTC->readMicroPC(); } 4225260Sksewell@umich.edu 4235592Sgblack@eecs.umich.edu void setNextMicroPC(uint64_t val) { actualTC->setNextMicroPC(val); } 4245260Sksewell@umich.edu 4254172Ssaidi@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg) 4264172Ssaidi@eecs.umich.edu { return actualTC->readMiscRegNoEffect(misc_reg); } 4274172Ssaidi@eecs.umich.edu 4282159SN/A MiscReg readMiscReg(int misc_reg) 4292680Sktlim@umich.edu { return actualTC->readMiscReg(misc_reg); } 4302SN/A 4314172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 4324172Ssaidi@eecs.umich.edu { return actualTC->setMiscRegNoEffect(misc_reg, val); } 4332SN/A 4343468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 4352680Sktlim@umich.edu { return actualTC->setMiscReg(misc_reg, val); } 4362SN/A 4372190SN/A unsigned readStCondFailures() 4382680Sktlim@umich.edu { return actualTC->readStCondFailures(); } 4392190SN/A 4402190SN/A void setStCondFailures(unsigned sc_failures) 4412680Sktlim@umich.edu { actualTC->setStCondFailures(sc_failures); } 4422SN/A 4432190SN/A // @todo: Fix this! 4442680Sktlim@umich.edu bool misspeculating() { return actualTC->misspeculating(); } 4452190SN/A 4461858SN/A#if !FULL_SYSTEM 4474111Sgblack@eecs.umich.edu void syscall(int64_t callnum) 4484111Sgblack@eecs.umich.edu { actualTC->syscall(callnum); } 4494111Sgblack@eecs.umich.edu 4502680Sktlim@umich.edu Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 4512SN/A#endif 4522SN/A}; 4532SN/A 4542190SN/A#endif 455