thread_context.hh revision 4172
12SN/A/* 22190SN/A * Copyright (c) 2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Kevin Lim 292SN/A */ 302SN/A 312680Sktlim@umich.edu#ifndef __CPU_THREAD_CONTEXT_HH__ 322680Sktlim@umich.edu#define __CPU_THREAD_CONTEXT_HH__ 332SN/A 342972Sgblack@eecs.umich.edu#include "arch/regfile.hh" 353453Sgblack@eecs.umich.edu#include "arch/types.hh" 361858SN/A#include "config/full_system.hh" 372423SN/A#include "mem/request.hh" 382190SN/A#include "sim/faults.hh" 3956SN/A#include "sim/host.hh" 40217SN/A#include "sim/serialize.hh" 413776Sgblack@eecs.umich.edu#include "sim/syscallreturn.hh" 422036SN/A#include "sim/byteswap.hh" 432SN/A 442190SN/A// @todo: Figure out a more architecture independent way to obtain the ITB and 452190SN/A// DTB pointers. 463453Sgblack@eecs.umich.edunamespace TheISA 473453Sgblack@eecs.umich.edu{ 483453Sgblack@eecs.umich.edu class DTB; 493453Sgblack@eecs.umich.edu class ITB; 503453Sgblack@eecs.umich.edu} 512190SN/Aclass BaseCPU; 522313SN/Aclass EndQuiesceEvent; 532235SN/Aclass Event; 542423SN/Aclass TranslatingPort; 552521SN/Aclass FunctionalPort; 562521SN/Aclass VirtualPort; 572190SN/Aclass Process; 582190SN/Aclass System; 593548Sgblack@eecs.umich.edunamespace TheISA { 603548Sgblack@eecs.umich.edu namespace Kernel { 613548Sgblack@eecs.umich.edu class Statistics; 623548Sgblack@eecs.umich.edu }; 632330SN/A}; 642SN/A 652680Sktlim@umich.edu/** 662680Sktlim@umich.edu * ThreadContext is the external interface to all thread state for 672680Sktlim@umich.edu * anything outside of the CPU. It provides all accessor methods to 682680Sktlim@umich.edu * state that might be needed by external objects, ranging from 692680Sktlim@umich.edu * register values to things such as kernel stats. It is an abstract 702680Sktlim@umich.edu * base class; the CPU can create its own ThreadContext by either 712680Sktlim@umich.edu * deriving from it, or using the templated ProxyThreadContext. 722680Sktlim@umich.edu * 732680Sktlim@umich.edu * The ThreadContext is slightly different than the ExecContext. The 742680Sktlim@umich.edu * ThreadContext provides access to an individual thread's state; an 752680Sktlim@umich.edu * ExecContext provides ISA access to the CPU (meaning it is 762682Sktlim@umich.edu * implicitly multithreaded on SMT systems). Additionally the 772680Sktlim@umich.edu * ThreadState is an abstract class that exactly defines the 782680Sktlim@umich.edu * interface; the ExecContext is a more implicit interface that must 792680Sktlim@umich.edu * be implemented so that the ISA can access whatever state it needs. 802680Sktlim@umich.edu */ 812680Sktlim@umich.educlass ThreadContext 822SN/A{ 832107SN/A protected: 842107SN/A typedef TheISA::RegFile RegFile; 852107SN/A typedef TheISA::MachInst MachInst; 862190SN/A typedef TheISA::IntReg IntReg; 872455SN/A typedef TheISA::FloatReg FloatReg; 882455SN/A typedef TheISA::FloatRegBits FloatRegBits; 892107SN/A typedef TheISA::MiscRegFile MiscRegFile; 902159SN/A typedef TheISA::MiscReg MiscReg; 912SN/A public: 92246SN/A enum Status 93246SN/A { 94246SN/A /// Initialized but not running yet. All CPUs start in 95246SN/A /// this state, but most transition to Active on cycle 1. 96246SN/A /// In MP or SMT systems, non-primary contexts will stay 97246SN/A /// in this state until a thread is assigned to them. 98246SN/A Unallocated, 99246SN/A 100246SN/A /// Running. Instructions should be executed only when 101246SN/A /// the context is in this state. 102246SN/A Active, 103246SN/A 104246SN/A /// Temporarily inactive. Entered while waiting for 1052190SN/A /// synchronization, etc. 106246SN/A Suspended, 107246SN/A 108246SN/A /// Permanently shut down. Entered when target executes 109246SN/A /// m5exit pseudo-instruction. When all contexts enter 110246SN/A /// this state, the simulation will terminate. 111246SN/A Halted 112246SN/A }; 1132SN/A 1142680Sktlim@umich.edu virtual ~ThreadContext() { }; 1152423SN/A 1162190SN/A virtual BaseCPU *getCpuPtr() = 0; 117180SN/A 1182190SN/A virtual void setCpuId(int id) = 0; 1192190SN/A 1202190SN/A virtual int readCpuId() = 0; 1212190SN/A 1222190SN/A#if FULL_SYSTEM 1232190SN/A virtual System *getSystemPtr() = 0; 1242190SN/A 1253453Sgblack@eecs.umich.edu virtual TheISA::ITB *getITBPtr() = 0; 1262190SN/A 1273453Sgblack@eecs.umich.edu virtual TheISA::DTB *getDTBPtr() = 0; 1282521SN/A 1293548Sgblack@eecs.umich.edu virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 1302654SN/A 1312521SN/A virtual FunctionalPort *getPhysPort() = 0; 1322521SN/A 1332680Sktlim@umich.edu virtual VirtualPort *getVirtPort(ThreadContext *tc = NULL) = 0; 1342521SN/A 1352521SN/A virtual void delVirtPort(VirtualPort *vp) = 0; 1363673Srdreslin@umich.edu 1373686Sktlim@umich.edu virtual void connectMemPorts() = 0; 1382190SN/A#else 1392518SN/A virtual TranslatingPort *getMemPort() = 0; 1402518SN/A 1412190SN/A virtual Process *getProcessPtr() = 0; 1422190SN/A#endif 1432190SN/A 1442190SN/A virtual Status status() const = 0; 1452159SN/A 1462235SN/A virtual void setStatus(Status new_status) = 0; 1472103SN/A 148393SN/A /// Set the status to Active. Optional delay indicates number of 149393SN/A /// cycles to wait before beginning execution. 1502190SN/A virtual void activate(int delay = 1) = 0; 151393SN/A 152393SN/A /// Set the status to Suspended. 1532190SN/A virtual void suspend() = 0; 154393SN/A 155393SN/A /// Set the status to Unallocated. 1562875Sksewell@umich.edu virtual void deallocate(int delay = 0) = 0; 157393SN/A 158393SN/A /// Set the status to Halted. 1592190SN/A virtual void halt() = 0; 1602159SN/A 1612159SN/A#if FULL_SYSTEM 1622190SN/A virtual void dumpFuncProfile() = 0; 1632159SN/A#endif 1642159SN/A 1652680Sktlim@umich.edu virtual void takeOverFrom(ThreadContext *old_context) = 0; 1662159SN/A 1672190SN/A virtual void regStats(const std::string &name) = 0; 1682159SN/A 1692190SN/A virtual void serialize(std::ostream &os) = 0; 1702190SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 1712159SN/A 1722235SN/A#if FULL_SYSTEM 1732313SN/A virtual EndQuiesceEvent *getQuiesceEvent() = 0; 1742235SN/A 1752235SN/A // Not necessarily the best location for these... 1762235SN/A // Having an extra function just to read these is obnoxious 1772235SN/A virtual Tick readLastActivate() = 0; 1782235SN/A virtual Tick readLastSuspend() = 0; 1792254SN/A 1802254SN/A virtual void profileClear() = 0; 1812254SN/A virtual void profileSample() = 0; 1822235SN/A#endif 1832235SN/A 1842190SN/A virtual int getThreadNum() = 0; 1852159SN/A 1862235SN/A // Also somewhat obnoxious. Really only used for the TLB fault. 1872254SN/A // However, may be quite useful in SPARC. 1882190SN/A virtual TheISA::MachInst getInst() = 0; 1892159SN/A 1902680Sktlim@umich.edu virtual void copyArchRegs(ThreadContext *tc) = 0; 1912159SN/A 1922190SN/A virtual void clearArchRegs() = 0; 1932159SN/A 1942159SN/A // 1952159SN/A // New accessors for new decoder. 1962159SN/A // 1972190SN/A virtual uint64_t readIntReg(int reg_idx) = 0; 1982159SN/A 1992455SN/A virtual FloatReg readFloatReg(int reg_idx, int width) = 0; 2002159SN/A 2012455SN/A virtual FloatReg readFloatReg(int reg_idx) = 0; 2022159SN/A 2032455SN/A virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0; 2042455SN/A 2052455SN/A virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 2062159SN/A 2072190SN/A virtual void setIntReg(int reg_idx, uint64_t val) = 0; 2082159SN/A 2092455SN/A virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0; 2102159SN/A 2112455SN/A virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 2122159SN/A 2132455SN/A virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 2142455SN/A 2152455SN/A virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0; 2162159SN/A 2172190SN/A virtual uint64_t readPC() = 0; 2182159SN/A 2192190SN/A virtual void setPC(uint64_t val) = 0; 2202159SN/A 2212190SN/A virtual uint64_t readNextPC() = 0; 2222159SN/A 2232190SN/A virtual void setNextPC(uint64_t val) = 0; 2242159SN/A 2252447SN/A virtual uint64_t readNextNPC() = 0; 2262447SN/A 2272447SN/A virtual void setNextNPC(uint64_t val) = 0; 2282447SN/A 2294172Ssaidi@eecs.umich.edu virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; 2304172Ssaidi@eecs.umich.edu 2312190SN/A virtual MiscReg readMiscReg(int misc_reg) = 0; 2322159SN/A 2334172Ssaidi@eecs.umich.edu virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; 2342190SN/A 2353468Sgblack@eecs.umich.edu virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 2362190SN/A 2372235SN/A // Also not necessarily the best location for these two. Hopefully will go 2382235SN/A // away once we decide upon where st cond failures goes. 2392190SN/A virtual unsigned readStCondFailures() = 0; 2402190SN/A 2412190SN/A virtual void setStCondFailures(unsigned sc_failures) = 0; 2422159SN/A 2432235SN/A // Only really makes sense for old CPU model. Still could be useful though. 2442190SN/A virtual bool misspeculating() = 0; 2452190SN/A 2462159SN/A#if !FULL_SYSTEM 2472190SN/A virtual IntReg getSyscallArg(int i) = 0; 2482159SN/A 2492159SN/A // used to shift args for indirect syscall 2502190SN/A virtual void setSyscallArg(int i, IntReg val) = 0; 2512159SN/A 2522190SN/A virtual void setSyscallReturn(SyscallReturn return_value) = 0; 2532159SN/A 2542235SN/A // Same with st cond failures. 2552190SN/A virtual Counter readFuncExeInst() = 0; 2562834Sksewell@umich.edu 2574111Sgblack@eecs.umich.edu virtual void syscall(int64_t callnum) = 0; 2584111Sgblack@eecs.umich.edu 2592834Sksewell@umich.edu // This function exits the thread context in the CPU and returns 2602834Sksewell@umich.edu // 1 if the CPU has no more active threads (meaning it's OK to exit); 2612834Sksewell@umich.edu // Used in syscall-emulation mode when a thread calls the exit syscall. 2622834Sksewell@umich.edu virtual int exit() { return 1; }; 2632159SN/A#endif 2642525SN/A 2652972Sgblack@eecs.umich.edu virtual void changeRegFileContext(TheISA::RegContextParam param, 2662972Sgblack@eecs.umich.edu TheISA::RegContextVal val) = 0; 2672159SN/A}; 2682159SN/A 2692682Sktlim@umich.edu/** 2702682Sktlim@umich.edu * ProxyThreadContext class that provides a way to implement a 2712682Sktlim@umich.edu * ThreadContext without having to derive from it. ThreadContext is an 2722682Sktlim@umich.edu * abstract class, so anything that derives from it and uses its 2732682Sktlim@umich.edu * interface will pay the overhead of virtual function calls. This 2742682Sktlim@umich.edu * class is created to enable a user-defined Thread object to be used 2752682Sktlim@umich.edu * wherever ThreadContexts are used, without paying the overhead of 2762682Sktlim@umich.edu * virtual function calls when it is used by itself. See 2772682Sktlim@umich.edu * simple_thread.hh for an example of this. 2782682Sktlim@umich.edu */ 2792680Sktlim@umich.edutemplate <class TC> 2802680Sktlim@umich.educlass ProxyThreadContext : public ThreadContext 2812190SN/A{ 2822190SN/A public: 2832680Sktlim@umich.edu ProxyThreadContext(TC *actual_tc) 2842680Sktlim@umich.edu { actualTC = actual_tc; } 2852159SN/A 2862190SN/A private: 2872680Sktlim@umich.edu TC *actualTC; 2882SN/A 2892SN/A public: 2902SN/A 2912680Sktlim@umich.edu BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 2922SN/A 2932680Sktlim@umich.edu void setCpuId(int id) { actualTC->setCpuId(id); } 294716SN/A 2952680Sktlim@umich.edu int readCpuId() { return actualTC->readCpuId(); } 2962SN/A 2971858SN/A#if FULL_SYSTEM 2982680Sktlim@umich.edu System *getSystemPtr() { return actualTC->getSystemPtr(); } 2992SN/A 3003453Sgblack@eecs.umich.edu TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); } 3011917SN/A 3023453Sgblack@eecs.umich.edu TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); } 3032521SN/A 3043548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *getKernelStats() 3053548Sgblack@eecs.umich.edu { return actualTC->getKernelStats(); } 3062654SN/A 3072680Sktlim@umich.edu FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); } 3082521SN/A 3092680Sktlim@umich.edu VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return actualTC->getVirtPort(tc); } 3102521SN/A 3112680Sktlim@umich.edu void delVirtPort(VirtualPort *vp) { return actualTC->delVirtPort(vp); } 3123673Srdreslin@umich.edu 3133686Sktlim@umich.edu void connectMemPorts() { actualTC->connectMemPorts(); } 3142SN/A#else 3152680Sktlim@umich.edu TranslatingPort *getMemPort() { return actualTC->getMemPort(); } 3162518SN/A 3172680Sktlim@umich.edu Process *getProcessPtr() { return actualTC->getProcessPtr(); } 3182SN/A#endif 3192SN/A 3202680Sktlim@umich.edu Status status() const { return actualTC->status(); } 321595SN/A 3222680Sktlim@umich.edu void setStatus(Status new_status) { actualTC->setStatus(new_status); } 3232SN/A 3242190SN/A /// Set the status to Active. Optional delay indicates number of 3252190SN/A /// cycles to wait before beginning execution. 3262680Sktlim@umich.edu void activate(int delay = 1) { actualTC->activate(delay); } 3272SN/A 3282190SN/A /// Set the status to Suspended. 3292680Sktlim@umich.edu void suspend() { actualTC->suspend(); } 3302SN/A 3312190SN/A /// Set the status to Unallocated. 3322875Sksewell@umich.edu void deallocate(int delay = 0) { actualTC->deallocate(); } 3332SN/A 3342190SN/A /// Set the status to Halted. 3352680Sktlim@umich.edu void halt() { actualTC->halt(); } 336217SN/A 3371858SN/A#if FULL_SYSTEM 3382680Sktlim@umich.edu void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 3392190SN/A#endif 3402190SN/A 3412680Sktlim@umich.edu void takeOverFrom(ThreadContext *oldContext) 3422680Sktlim@umich.edu { actualTC->takeOverFrom(oldContext); } 3432190SN/A 3442680Sktlim@umich.edu void regStats(const std::string &name) { actualTC->regStats(name); } 3452190SN/A 3462680Sktlim@umich.edu void serialize(std::ostream &os) { actualTC->serialize(os); } 3472190SN/A void unserialize(Checkpoint *cp, const std::string §ion) 3482680Sktlim@umich.edu { actualTC->unserialize(cp, section); } 3492190SN/A 3502235SN/A#if FULL_SYSTEM 3512680Sktlim@umich.edu EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 3522235SN/A 3532680Sktlim@umich.edu Tick readLastActivate() { return actualTC->readLastActivate(); } 3542680Sktlim@umich.edu Tick readLastSuspend() { return actualTC->readLastSuspend(); } 3552254SN/A 3562680Sktlim@umich.edu void profileClear() { return actualTC->profileClear(); } 3572680Sktlim@umich.edu void profileSample() { return actualTC->profileSample(); } 3582235SN/A#endif 3592235SN/A 3602680Sktlim@umich.edu int getThreadNum() { return actualTC->getThreadNum(); } 3612190SN/A 3622190SN/A // @todo: Do I need this? 3632680Sktlim@umich.edu MachInst getInst() { return actualTC->getInst(); } 3642SN/A 3652190SN/A // @todo: Do I need this? 3662680Sktlim@umich.edu void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 3672SN/A 3682680Sktlim@umich.edu void clearArchRegs() { actualTC->clearArchRegs(); } 369716SN/A 3702SN/A // 3712SN/A // New accessors for new decoder. 3722SN/A // 3732SN/A uint64_t readIntReg(int reg_idx) 3742680Sktlim@umich.edu { return actualTC->readIntReg(reg_idx); } 3752SN/A 3762455SN/A FloatReg readFloatReg(int reg_idx, int width) 3772680Sktlim@umich.edu { return actualTC->readFloatReg(reg_idx, width); } 3782SN/A 3792455SN/A FloatReg readFloatReg(int reg_idx) 3802680Sktlim@umich.edu { return actualTC->readFloatReg(reg_idx); } 3812SN/A 3822455SN/A FloatRegBits readFloatRegBits(int reg_idx, int width) 3832680Sktlim@umich.edu { return actualTC->readFloatRegBits(reg_idx, width); } 3842455SN/A 3852455SN/A FloatRegBits readFloatRegBits(int reg_idx) 3862680Sktlim@umich.edu { return actualTC->readFloatRegBits(reg_idx); } 3872SN/A 3882SN/A void setIntReg(int reg_idx, uint64_t val) 3892680Sktlim@umich.edu { actualTC->setIntReg(reg_idx, val); } 3902SN/A 3912455SN/A void setFloatReg(int reg_idx, FloatReg val, int width) 3922680Sktlim@umich.edu { actualTC->setFloatReg(reg_idx, val, width); } 3932SN/A 3942455SN/A void setFloatReg(int reg_idx, FloatReg val) 3952680Sktlim@umich.edu { actualTC->setFloatReg(reg_idx, val); } 3962SN/A 3972455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 3982680Sktlim@umich.edu { actualTC->setFloatRegBits(reg_idx, val, width); } 3992455SN/A 4002455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 4012680Sktlim@umich.edu { actualTC->setFloatRegBits(reg_idx, val); } 4022SN/A 4032680Sktlim@umich.edu uint64_t readPC() { return actualTC->readPC(); } 4042SN/A 4052680Sktlim@umich.edu void setPC(uint64_t val) { actualTC->setPC(val); } 4062206SN/A 4072680Sktlim@umich.edu uint64_t readNextPC() { return actualTC->readNextPC(); } 4082252SN/A 4092680Sktlim@umich.edu void setNextPC(uint64_t val) { actualTC->setNextPC(val); } 4102SN/A 4112680Sktlim@umich.edu uint64_t readNextNPC() { return actualTC->readNextNPC(); } 4122447SN/A 4132680Sktlim@umich.edu void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); } 4142447SN/A 4154172Ssaidi@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg) 4164172Ssaidi@eecs.umich.edu { return actualTC->readMiscRegNoEffect(misc_reg); } 4174172Ssaidi@eecs.umich.edu 4182159SN/A MiscReg readMiscReg(int misc_reg) 4192680Sktlim@umich.edu { return actualTC->readMiscReg(misc_reg); } 4202SN/A 4214172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 4224172Ssaidi@eecs.umich.edu { return actualTC->setMiscRegNoEffect(misc_reg, val); } 4232SN/A 4243468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 4252680Sktlim@umich.edu { return actualTC->setMiscReg(misc_reg, val); } 4262SN/A 4272190SN/A unsigned readStCondFailures() 4282680Sktlim@umich.edu { return actualTC->readStCondFailures(); } 4292190SN/A 4302190SN/A void setStCondFailures(unsigned sc_failures) 4312680Sktlim@umich.edu { actualTC->setStCondFailures(sc_failures); } 4322SN/A 4332190SN/A // @todo: Fix this! 4342680Sktlim@umich.edu bool misspeculating() { return actualTC->misspeculating(); } 4352190SN/A 4361858SN/A#if !FULL_SYSTEM 4372680Sktlim@umich.edu IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); } 438360SN/A 439360SN/A // used to shift args for indirect syscall 4402190SN/A void setSyscallArg(int i, IntReg val) 4412680Sktlim@umich.edu { actualTC->setSyscallArg(i, val); } 442360SN/A 4431450SN/A void setSyscallReturn(SyscallReturn return_value) 4442680Sktlim@umich.edu { actualTC->setSyscallReturn(return_value); } 445360SN/A 4464111Sgblack@eecs.umich.edu void syscall(int64_t callnum) 4474111Sgblack@eecs.umich.edu { actualTC->syscall(callnum); } 4484111Sgblack@eecs.umich.edu 4492680Sktlim@umich.edu Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 4502SN/A#endif 4512525SN/A 4522972Sgblack@eecs.umich.edu void changeRegFileContext(TheISA::RegContextParam param, 4532972Sgblack@eecs.umich.edu TheISA::RegContextVal val) 4542525SN/A { 4552680Sktlim@umich.edu actualTC->changeRegFileContext(param, val); 4562525SN/A } 4572SN/A}; 4582SN/A 4592190SN/A#endif 460