thread_context.hh revision 393
1/* 2 * Copyright (c) 2003 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __EXEC_CONTEXT_HH__ 30#define __EXEC_CONTEXT_HH__ 31 32#include "sim/host.hh" 33#include "mem/mem_req.hh" 34#include "sim/serialize.hh" 35 36// forward declaration: see functional_memory.hh 37class FunctionalMemory; 38class PhysicalMemory; 39class BaseCPU; 40 41#ifdef FULL_SYSTEM 42 43#include "targetarch/alpha_memory.hh" 44class MemoryController; 45 46#include "kern/tru64/kernel_stats.hh" 47#include "sim/system.hh" 48 49#ifdef FS_MEASURE 50#include "sim/sw_context.hh" 51#endif 52 53#else // !FULL_SYSTEM 54 55#include "sim/process.hh" 56 57#endif // FULL_SYSTEM 58 59// 60// The ExecContext object represents a functional context for 61// instruction execution. It incorporates everything required for 62// architecture-level functional simulation of a single thread. 63// 64 65class ExecContext 66{ 67 public: 68 enum Status 69 { 70 /// Initialized but not running yet. All CPUs start in 71 /// this state, but most transition to Active on cycle 1. 72 /// In MP or SMT systems, non-primary contexts will stay 73 /// in this state until a thread is assigned to them. 74 Unallocated, 75 76 /// Running. Instructions should be executed only when 77 /// the context is in this state. 78 Active, 79 80 /// Temporarily inactive. Entered while waiting for 81 /// synchronization, etc. 82 Suspended, 83 84 /// Permanently shut down. Entered when target executes 85 /// m5exit pseudo-instruction. When all contexts enter 86 /// this state, the simulation will terminate. 87 Halted 88 }; 89 90 private: 91 Status _status; 92 93 public: 94 Status status() const { return _status; } 95 96 /// Set the status to Active. Optional delay indicates number of 97 /// cycles to wait before beginning execution. 98 void activate(int delay = 1); 99 100 /// Set the status to Suspended. 101 void suspend(); 102 103 /// Set the status to Unallocated. 104 void deallocate(); 105 106 /// Set the status to Halted. 107 void halt(); 108 109#ifdef FULL_SYSTEM 110 public: 111 KernelStats kernelStats; 112#endif 113 114 public: 115 RegFile regs; // correct-path register context 116 117 // pointer to CPU associated with this context 118 BaseCPU *cpu; 119 120 // Index of hardware thread context on the CPU that this represents. 121 int thread_num; 122 123 // ID of this context w.r.t. the System or Process object to which 124 // it belongs. For full-system mode, this is the system CPU ID. 125 int cpu_id; 126 127#ifdef FULL_SYSTEM 128 129 FunctionalMemory *mem; 130 AlphaItb *itb; 131 AlphaDtb *dtb; 132 System *system; 133 134 // the following two fields are redundant, since we can always 135 // look them up through the system pointer, but we'll leave them 136 // here for now for convenience 137 MemoryController *memCtrl; 138 PhysicalMemory *physmem; 139 140#ifdef FS_MEASURE 141 SWContext *swCtx; 142#endif 143 144#else 145 Process *process; 146 147 FunctionalMemory *mem; // functional storage for process address space 148 149 // Address space ID. Note that this is used for TIMING cache 150 // simulation only; all functional memory accesses should use 151 // one of the FunctionalMemory pointers above. 152 short asid; 153 154#endif 155 156 157 /* 158 * number of executed instructions, for matching with syscall trace 159 * points in EIO files. 160 */ 161 Counter func_exe_insn; 162 163 // 164 // Count failed store conditionals so we can warn of apparent 165 // application deadlock situations. 166 unsigned storeCondFailures; 167 168 // constructor: initialize context from given process structure 169#ifdef FULL_SYSTEM 170 ExecContext(BaseCPU *_cpu, int _thread_num, System *_system, 171 AlphaItb *_itb, AlphaDtb *_dtb, FunctionalMemory *_dem); 172#else 173 ExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid); 174 ExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem, 175 int _asid); 176#endif 177 virtual ~ExecContext() {} 178 179 virtual void takeOverFrom(ExecContext *oldContext); 180 181 void regStats(const std::string &name); 182 183 void serialize(std::ostream &os); 184 void unserialize(Checkpoint *cp, const std::string §ion); 185 186#ifdef FULL_SYSTEM 187 bool validInstAddr(Addr addr) { return true; } 188 bool validDataAddr(Addr addr) { return true; } 189 int getInstAsid() { return ITB_ASN_ASN(regs.ipr[TheISA::IPR_ITB_ASN]); } 190 int getDataAsid() { return DTB_ASN_ASN(regs.ipr[TheISA::IPR_DTB_ASN]); } 191 192 Fault translateInstReq(MemReqPtr req) 193 { 194 return itb->translate(req); 195 } 196 197 Fault translateDataReadReq(MemReqPtr req) 198 { 199 return dtb->translate(req, false); 200 } 201 202 Fault translateDataWriteReq(MemReqPtr req) 203 { 204 return dtb->translate(req, true); 205 } 206 207#else 208 bool validInstAddr(Addr addr) 209 { return process->validInstAddr(addr); } 210 211 bool validDataAddr(Addr addr) 212 { return process->validDataAddr(addr); } 213 214 int getInstAsid() { return asid; } 215 int getDataAsid() { return asid; } 216 217 Fault dummyTranslation(MemReqPtr req) 218 { 219#if 0 220 assert((req->vaddr >> 48 & 0xffff) == 0); 221#endif 222 223 // put the asid in the upper 16 bits of the paddr 224 req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16); 225 req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16; 226 return No_Fault; 227 } 228 Fault translateInstReq(MemReqPtr req) 229 { 230 return dummyTranslation(req); 231 } 232 Fault translateDataReadReq(MemReqPtr req) 233 { 234 return dummyTranslation(req); 235 } 236 Fault translateDataWriteReq(MemReqPtr req) 237 { 238 return dummyTranslation(req); 239 } 240 241#endif 242 243 template <class T> 244 Fault read(MemReqPtr req, T& data) 245 { 246#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM) 247 if (req->flags & LOCKED) { 248 MiscRegFile *cregs = &req->xc->regs.miscRegs; 249 cregs->lock_addr = req->paddr; 250 cregs->lock_flag = true; 251 } 252#endif 253 return mem->read(req, data); 254 } 255 256 template <class T> 257 Fault write(MemReqPtr req, T& data) 258 { 259#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM) 260 261 MiscRegFile *cregs; 262 263 // If this is a store conditional, act appropriately 264 if (req->flags & LOCKED) { 265 cregs = &req->xc->regs.miscRegs; 266 267 if (req->flags & UNCACHEABLE) { 268 // Don't update result register (see stq_c in isa_desc) 269 req->result = 2; 270 req->xc->storeCondFailures = 0;//Needed? [RGD] 271 } else { 272 req->result = cregs->lock_flag; 273 if (!cregs->lock_flag || 274 ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) { 275 cregs->lock_flag = false; 276 if (((++req->xc->storeCondFailures) % 100000) == 0) { 277 std::cerr << "Warning: " 278 << req->xc->storeCondFailures 279 << " consecutive store conditional failures " 280 << "on cpu " << req->xc->cpu_id 281 << std::endl; 282 } 283 return No_Fault; 284 } 285 else req->xc->storeCondFailures = 0; 286 } 287 } 288 289 // Need to clear any locked flags on other proccessors for 290 // this address. Only do this for succsful Store Conditionals 291 // and all other stores (WH64?). Unsuccessful Store 292 // Conditionals would have returned above, and wouldn't fall 293 // through. 294 for (int i = 0; i < system->execContexts.size(); i++){ 295 cregs = &system->execContexts[i]->regs.miscRegs; 296 if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) { 297 cregs->lock_flag = false; 298 } 299 } 300 301#endif 302 return mem->write(req, data); 303 } 304 305 virtual bool misspeculating(); 306 307 308 // 309 // New accessors for new decoder. 310 // 311 uint64_t readIntReg(int reg_idx) 312 { 313 return regs.intRegFile[reg_idx]; 314 } 315 316 float readFloatRegSingle(int reg_idx) 317 { 318 return (float)regs.floatRegFile.d[reg_idx]; 319 } 320 321 double readFloatRegDouble(int reg_idx) 322 { 323 return regs.floatRegFile.d[reg_idx]; 324 } 325 326 uint64_t readFloatRegInt(int reg_idx) 327 { 328 return regs.floatRegFile.q[reg_idx]; 329 } 330 331 void setIntReg(int reg_idx, uint64_t val) 332 { 333 regs.intRegFile[reg_idx] = val; 334 } 335 336 void setFloatRegSingle(int reg_idx, float val) 337 { 338 regs.floatRegFile.d[reg_idx] = (double)val; 339 } 340 341 void setFloatRegDouble(int reg_idx, double val) 342 { 343 regs.floatRegFile.d[reg_idx] = val; 344 } 345 346 void setFloatRegInt(int reg_idx, uint64_t val) 347 { 348 regs.floatRegFile.q[reg_idx] = val; 349 } 350 351 uint64_t readPC() 352 { 353 return regs.pc; 354 } 355 356 void setNextPC(uint64_t val) 357 { 358 regs.npc = val; 359 } 360 361 uint64_t readUniq() 362 { 363 return regs.miscRegs.uniq; 364 } 365 366 void setUniq(uint64_t val) 367 { 368 regs.miscRegs.uniq = val; 369 } 370 371 uint64_t readFpcr() 372 { 373 return regs.miscRegs.fpcr; 374 } 375 376 void setFpcr(uint64_t val) 377 { 378 regs.miscRegs.fpcr = val; 379 } 380 381#ifdef FULL_SYSTEM 382 uint64_t readIpr(int idx, Fault &fault); 383 Fault setIpr(int idx, uint64_t val); 384 Fault hwrei(); 385 void ev5_trap(Fault fault); 386 bool simPalCheck(int palFunc); 387#endif 388 389#ifndef FULL_SYSTEM 390 IntReg getSyscallArg(int i) 391 { 392 return regs.intRegFile[ArgumentReg0 + i]; 393 } 394 395 // used to shift args for indirect syscall 396 void setSyscallArg(int i, IntReg val) 397 { 398 regs.intRegFile[ArgumentReg0 + i] = val; 399 } 400 401 void setSyscallReturn(int64_t return_value) 402 { 403 // check for error condition. Alpha syscall convention is to 404 // indicate success/failure in reg a3 (r19) and put the 405 // return value itself in the standard return value reg (v0). 406 const int RegA3 = 19; // only place this is used 407 if (return_value >= 0) { 408 // no error 409 regs.intRegFile[RegA3] = 0; 410 regs.intRegFile[ReturnValueReg] = return_value; 411 } else { 412 // got an error, return details 413 regs.intRegFile[RegA3] = (IntReg) -1; 414 regs.intRegFile[ReturnValueReg] = -return_value; 415 } 416 } 417 418 void syscall() 419 { 420 process->syscall(this); 421 } 422#endif 423}; 424 425 426// for non-speculative execution context, spec_mode is always false 427inline bool 428ExecContext::misspeculating() 429{ 430 return false; 431} 432 433#endif // __EXEC_CONTEXT_HH__ 434