thread_context.hh revision 2817
12SN/A/* 22190SN/A * Copyright (c) 2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Kevin Lim 292SN/A */ 302SN/A 312680Sktlim@umich.edu#ifndef __CPU_THREAD_CONTEXT_HH__ 322680Sktlim@umich.edu#define __CPU_THREAD_CONTEXT_HH__ 332SN/A 341858SN/A#include "config/full_system.hh" 352423SN/A#include "mem/request.hh" 362190SN/A#include "sim/faults.hh" 3756SN/A#include "sim/host.hh" 38217SN/A#include "sim/serialize.hh" 392036SN/A#include "sim/byteswap.hh" 402SN/A 412190SN/A// @todo: Figure out a more architecture independent way to obtain the ITB and 422190SN/A// DTB pointers. 432190SN/Aclass AlphaDTB; 442190SN/Aclass AlphaITB; 452190SN/Aclass BaseCPU; 462313SN/Aclass EndQuiesceEvent; 472235SN/Aclass Event; 482423SN/Aclass TranslatingPort; 492521SN/Aclass FunctionalPort; 502521SN/Aclass VirtualPort; 512190SN/Aclass Process; 522190SN/Aclass System; 532330SN/Anamespace Kernel { 542330SN/A class Statistics; 552330SN/A}; 562SN/A 572680Sktlim@umich.edu/** 582680Sktlim@umich.edu * ThreadContext is the external interface to all thread state for 592680Sktlim@umich.edu * anything outside of the CPU. It provides all accessor methods to 602680Sktlim@umich.edu * state that might be needed by external objects, ranging from 612680Sktlim@umich.edu * register values to things such as kernel stats. It is an abstract 622680Sktlim@umich.edu * base class; the CPU can create its own ThreadContext by either 632680Sktlim@umich.edu * deriving from it, or using the templated ProxyThreadContext. 642680Sktlim@umich.edu * 652680Sktlim@umich.edu * The ThreadContext is slightly different than the ExecContext. The 662680Sktlim@umich.edu * ThreadContext provides access to an individual thread's state; an 672680Sktlim@umich.edu * ExecContext provides ISA access to the CPU (meaning it is 682682Sktlim@umich.edu * implicitly multithreaded on SMT systems). Additionally the 692680Sktlim@umich.edu * ThreadState is an abstract class that exactly defines the 702680Sktlim@umich.edu * interface; the ExecContext is a more implicit interface that must 712680Sktlim@umich.edu * be implemented so that the ISA can access whatever state it needs. 722680Sktlim@umich.edu */ 732680Sktlim@umich.educlass ThreadContext 742SN/A{ 752107SN/A protected: 762107SN/A typedef TheISA::RegFile RegFile; 772107SN/A typedef TheISA::MachInst MachInst; 782190SN/A typedef TheISA::IntReg IntReg; 792455SN/A typedef TheISA::FloatReg FloatReg; 802455SN/A typedef TheISA::FloatRegBits FloatRegBits; 812107SN/A typedef TheISA::MiscRegFile MiscRegFile; 822159SN/A typedef TheISA::MiscReg MiscReg; 832SN/A public: 84246SN/A enum Status 85246SN/A { 86246SN/A /// Initialized but not running yet. All CPUs start in 87246SN/A /// this state, but most transition to Active on cycle 1. 88246SN/A /// In MP or SMT systems, non-primary contexts will stay 89246SN/A /// in this state until a thread is assigned to them. 90246SN/A Unallocated, 91246SN/A 92246SN/A /// Running. Instructions should be executed only when 93246SN/A /// the context is in this state. 94246SN/A Active, 95246SN/A 96246SN/A /// Temporarily inactive. Entered while waiting for 972190SN/A /// synchronization, etc. 98246SN/A Suspended, 99246SN/A 100246SN/A /// Permanently shut down. Entered when target executes 101246SN/A /// m5exit pseudo-instruction. When all contexts enter 102246SN/A /// this state, the simulation will terminate. 103246SN/A Halted 104246SN/A }; 1052SN/A 1062680Sktlim@umich.edu virtual ~ThreadContext() { }; 1072423SN/A 1082190SN/A virtual BaseCPU *getCpuPtr() = 0; 109180SN/A 1102190SN/A virtual void setCpuId(int id) = 0; 1112190SN/A 1122190SN/A virtual int readCpuId() = 0; 1132190SN/A 1142190SN/A#if FULL_SYSTEM 1152190SN/A virtual System *getSystemPtr() = 0; 1162190SN/A 1172190SN/A virtual AlphaITB *getITBPtr() = 0; 1182190SN/A 1192190SN/A virtual AlphaDTB * getDTBPtr() = 0; 1202521SN/A 1212330SN/A virtual Kernel::Statistics *getKernelStats() = 0; 1222654SN/A 1232521SN/A virtual FunctionalPort *getPhysPort() = 0; 1242521SN/A 1252680Sktlim@umich.edu virtual VirtualPort *getVirtPort(ThreadContext *tc = NULL) = 0; 1262521SN/A 1272521SN/A virtual void delVirtPort(VirtualPort *vp) = 0; 1282190SN/A#else 1292518SN/A virtual TranslatingPort *getMemPort() = 0; 1302518SN/A 1312190SN/A virtual Process *getProcessPtr() = 0; 1322190SN/A#endif 1332190SN/A 1342190SN/A virtual Status status() const = 0; 1352159SN/A 1362235SN/A virtual void setStatus(Status new_status) = 0; 1372103SN/A 138393SN/A /// Set the status to Active. Optional delay indicates number of 139393SN/A /// cycles to wait before beginning execution. 1402190SN/A virtual void activate(int delay = 1) = 0; 141393SN/A 142393SN/A /// Set the status to Suspended. 1432190SN/A virtual void suspend() = 0; 144393SN/A 145393SN/A /// Set the status to Unallocated. 1462190SN/A virtual void deallocate() = 0; 147393SN/A 148393SN/A /// Set the status to Halted. 1492190SN/A virtual void halt() = 0; 1502159SN/A 1512159SN/A#if FULL_SYSTEM 1522190SN/A virtual void dumpFuncProfile() = 0; 1532159SN/A#endif 1542159SN/A 1552680Sktlim@umich.edu virtual void takeOverFrom(ThreadContext *old_context) = 0; 1562159SN/A 1572190SN/A virtual void regStats(const std::string &name) = 0; 1582159SN/A 1592190SN/A virtual void serialize(std::ostream &os) = 0; 1602190SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 1612159SN/A 1622235SN/A#if FULL_SYSTEM 1632313SN/A virtual EndQuiesceEvent *getQuiesceEvent() = 0; 1642235SN/A 1652235SN/A // Not necessarily the best location for these... 1662235SN/A // Having an extra function just to read these is obnoxious 1672235SN/A virtual Tick readLastActivate() = 0; 1682235SN/A virtual Tick readLastSuspend() = 0; 1692254SN/A 1702254SN/A virtual void profileClear() = 0; 1712254SN/A virtual void profileSample() = 0; 1722235SN/A#endif 1732235SN/A 1742190SN/A virtual int getThreadNum() = 0; 1752159SN/A 1762235SN/A // Also somewhat obnoxious. Really only used for the TLB fault. 1772254SN/A // However, may be quite useful in SPARC. 1782190SN/A virtual TheISA::MachInst getInst() = 0; 1792159SN/A 1802680Sktlim@umich.edu virtual void copyArchRegs(ThreadContext *tc) = 0; 1812159SN/A 1822190SN/A virtual void clearArchRegs() = 0; 1832159SN/A 1842159SN/A // 1852159SN/A // New accessors for new decoder. 1862159SN/A // 1872190SN/A virtual uint64_t readIntReg(int reg_idx) = 0; 1882159SN/A 1892455SN/A virtual FloatReg readFloatReg(int reg_idx, int width) = 0; 1902159SN/A 1912455SN/A virtual FloatReg readFloatReg(int reg_idx) = 0; 1922159SN/A 1932455SN/A virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0; 1942455SN/A 1952455SN/A virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 1962159SN/A 1972190SN/A virtual void setIntReg(int reg_idx, uint64_t val) = 0; 1982159SN/A 1992455SN/A virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0; 2002159SN/A 2012455SN/A virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 2022159SN/A 2032455SN/A virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 2042455SN/A 2052455SN/A virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0; 2062159SN/A 2072190SN/A virtual uint64_t readPC() = 0; 2082159SN/A 2092190SN/A virtual void setPC(uint64_t val) = 0; 2102159SN/A 2112190SN/A virtual uint64_t readNextPC() = 0; 2122159SN/A 2132190SN/A virtual void setNextPC(uint64_t val) = 0; 2142159SN/A 2152447SN/A virtual uint64_t readNextNPC() = 0; 2162447SN/A 2172447SN/A virtual void setNextNPC(uint64_t val) = 0; 2182447SN/A 2192190SN/A virtual MiscReg readMiscReg(int misc_reg) = 0; 2202159SN/A 2212190SN/A virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) = 0; 2222190SN/A 2232190SN/A virtual Fault setMiscReg(int misc_reg, const MiscReg &val) = 0; 2242190SN/A 2252190SN/A virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0; 2262190SN/A 2272235SN/A // Also not necessarily the best location for these two. Hopefully will go 2282235SN/A // away once we decide upon where st cond failures goes. 2292190SN/A virtual unsigned readStCondFailures() = 0; 2302190SN/A 2312190SN/A virtual void setStCondFailures(unsigned sc_failures) = 0; 2322159SN/A 2332159SN/A#if FULL_SYSTEM 2342190SN/A virtual bool inPalMode() = 0; 2352159SN/A#endif 2362159SN/A 2372235SN/A // Only really makes sense for old CPU model. Still could be useful though. 2382190SN/A virtual bool misspeculating() = 0; 2392190SN/A 2402159SN/A#if !FULL_SYSTEM 2412190SN/A virtual IntReg getSyscallArg(int i) = 0; 2422159SN/A 2432159SN/A // used to shift args for indirect syscall 2442190SN/A virtual void setSyscallArg(int i, IntReg val) = 0; 2452159SN/A 2462190SN/A virtual void setSyscallReturn(SyscallReturn return_value) = 0; 2472159SN/A 2482235SN/A // Same with st cond failures. 2492190SN/A virtual Counter readFuncExeInst() = 0; 2502159SN/A#endif 2512525SN/A 2522525SN/A virtual void changeRegFileContext(RegFile::ContextParam param, 2532525SN/A RegFile::ContextVal val) = 0; 2542159SN/A}; 2552159SN/A 2562682Sktlim@umich.edu/** 2572682Sktlim@umich.edu * ProxyThreadContext class that provides a way to implement a 2582682Sktlim@umich.edu * ThreadContext without having to derive from it. ThreadContext is an 2592682Sktlim@umich.edu * abstract class, so anything that derives from it and uses its 2602682Sktlim@umich.edu * interface will pay the overhead of virtual function calls. This 2612682Sktlim@umich.edu * class is created to enable a user-defined Thread object to be used 2622682Sktlim@umich.edu * wherever ThreadContexts are used, without paying the overhead of 2632682Sktlim@umich.edu * virtual function calls when it is used by itself. See 2642682Sktlim@umich.edu * simple_thread.hh for an example of this. 2652682Sktlim@umich.edu */ 2662680Sktlim@umich.edutemplate <class TC> 2672680Sktlim@umich.educlass ProxyThreadContext : public ThreadContext 2682190SN/A{ 2692190SN/A public: 2702680Sktlim@umich.edu ProxyThreadContext(TC *actual_tc) 2712680Sktlim@umich.edu { actualTC = actual_tc; } 2722159SN/A 2732190SN/A private: 2742680Sktlim@umich.edu TC *actualTC; 2752SN/A 2762SN/A public: 2772SN/A 2782680Sktlim@umich.edu BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 2792SN/A 2802680Sktlim@umich.edu void setCpuId(int id) { actualTC->setCpuId(id); } 281716SN/A 2822680Sktlim@umich.edu int readCpuId() { return actualTC->readCpuId(); } 2832SN/A 2841858SN/A#if FULL_SYSTEM 2852680Sktlim@umich.edu System *getSystemPtr() { return actualTC->getSystemPtr(); } 2862SN/A 2872680Sktlim@umich.edu AlphaITB *getITBPtr() { return actualTC->getITBPtr(); } 2881917SN/A 2892680Sktlim@umich.edu AlphaDTB *getDTBPtr() { return actualTC->getDTBPtr(); } 2902521SN/A 2912680Sktlim@umich.edu Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); } 2922654SN/A 2932680Sktlim@umich.edu FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); } 2942521SN/A 2952680Sktlim@umich.edu VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return actualTC->getVirtPort(tc); } 2962521SN/A 2972680Sktlim@umich.edu void delVirtPort(VirtualPort *vp) { return actualTC->delVirtPort(vp); } 2982SN/A#else 2992680Sktlim@umich.edu TranslatingPort *getMemPort() { return actualTC->getMemPort(); } 3002518SN/A 3012680Sktlim@umich.edu Process *getProcessPtr() { return actualTC->getProcessPtr(); } 3022SN/A#endif 3032SN/A 3042680Sktlim@umich.edu Status status() const { return actualTC->status(); } 305595SN/A 3062680Sktlim@umich.edu void setStatus(Status new_status) { actualTC->setStatus(new_status); } 3072SN/A 3082190SN/A /// Set the status to Active. Optional delay indicates number of 3092190SN/A /// cycles to wait before beginning execution. 3102680Sktlim@umich.edu void activate(int delay = 1) { actualTC->activate(delay); } 3112SN/A 3122190SN/A /// Set the status to Suspended. 3132680Sktlim@umich.edu void suspend() { actualTC->suspend(); } 3142SN/A 3152190SN/A /// Set the status to Unallocated. 3162680Sktlim@umich.edu void deallocate() { actualTC->deallocate(); } 3172SN/A 3182190SN/A /// Set the status to Halted. 3192680Sktlim@umich.edu void halt() { actualTC->halt(); } 320217SN/A 3211858SN/A#if FULL_SYSTEM 3222680Sktlim@umich.edu void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 3232190SN/A#endif 3242190SN/A 3252680Sktlim@umich.edu void takeOverFrom(ThreadContext *oldContext) 3262680Sktlim@umich.edu { actualTC->takeOverFrom(oldContext); } 3272190SN/A 3282680Sktlim@umich.edu void regStats(const std::string &name) { actualTC->regStats(name); } 3292190SN/A 3302680Sktlim@umich.edu void serialize(std::ostream &os) { actualTC->serialize(os); } 3312190SN/A void unserialize(Checkpoint *cp, const std::string §ion) 3322680Sktlim@umich.edu { actualTC->unserialize(cp, section); } 3332190SN/A 3342235SN/A#if FULL_SYSTEM 3352680Sktlim@umich.edu EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 3362235SN/A 3372680Sktlim@umich.edu Tick readLastActivate() { return actualTC->readLastActivate(); } 3382680Sktlim@umich.edu Tick readLastSuspend() { return actualTC->readLastSuspend(); } 3392254SN/A 3402680Sktlim@umich.edu void profileClear() { return actualTC->profileClear(); } 3412680Sktlim@umich.edu void profileSample() { return actualTC->profileSample(); } 3422235SN/A#endif 3432235SN/A 3442680Sktlim@umich.edu int getThreadNum() { return actualTC->getThreadNum(); } 3452190SN/A 3462190SN/A // @todo: Do I need this? 3472680Sktlim@umich.edu MachInst getInst() { return actualTC->getInst(); } 3482SN/A 3492190SN/A // @todo: Do I need this? 3502680Sktlim@umich.edu void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 3512SN/A 3522680Sktlim@umich.edu void clearArchRegs() { actualTC->clearArchRegs(); } 353716SN/A 3542SN/A // 3552SN/A // New accessors for new decoder. 3562SN/A // 3572SN/A uint64_t readIntReg(int reg_idx) 3582680Sktlim@umich.edu { return actualTC->readIntReg(reg_idx); } 3592SN/A 3602455SN/A FloatReg readFloatReg(int reg_idx, int width) 3612680Sktlim@umich.edu { return actualTC->readFloatReg(reg_idx, width); } 3622SN/A 3632455SN/A FloatReg readFloatReg(int reg_idx) 3642680Sktlim@umich.edu { return actualTC->readFloatReg(reg_idx); } 3652SN/A 3662455SN/A FloatRegBits readFloatRegBits(int reg_idx, int width) 3672680Sktlim@umich.edu { return actualTC->readFloatRegBits(reg_idx, width); } 3682455SN/A 3692455SN/A FloatRegBits readFloatRegBits(int reg_idx) 3702680Sktlim@umich.edu { return actualTC->readFloatRegBits(reg_idx); } 3712SN/A 3722SN/A void setIntReg(int reg_idx, uint64_t val) 3732680Sktlim@umich.edu { actualTC->setIntReg(reg_idx, val); } 3742SN/A 3752455SN/A void setFloatReg(int reg_idx, FloatReg val, int width) 3762680Sktlim@umich.edu { actualTC->setFloatReg(reg_idx, val, width); } 3772SN/A 3782455SN/A void setFloatReg(int reg_idx, FloatReg val) 3792680Sktlim@umich.edu { actualTC->setFloatReg(reg_idx, val); } 3802SN/A 3812455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 3822680Sktlim@umich.edu { actualTC->setFloatRegBits(reg_idx, val, width); } 3832455SN/A 3842455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 3852680Sktlim@umich.edu { actualTC->setFloatRegBits(reg_idx, val); } 3862SN/A 3872680Sktlim@umich.edu uint64_t readPC() { return actualTC->readPC(); } 3882SN/A 3892680Sktlim@umich.edu void setPC(uint64_t val) { actualTC->setPC(val); } 3902206SN/A 3912680Sktlim@umich.edu uint64_t readNextPC() { return actualTC->readNextPC(); } 3922252SN/A 3932680Sktlim@umich.edu void setNextPC(uint64_t val) { actualTC->setNextPC(val); } 3942SN/A 3952680Sktlim@umich.edu uint64_t readNextNPC() { return actualTC->readNextNPC(); } 3962447SN/A 3972680Sktlim@umich.edu void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); } 3982447SN/A 3992159SN/A MiscReg readMiscReg(int misc_reg) 4002680Sktlim@umich.edu { return actualTC->readMiscReg(misc_reg); } 4012SN/A 4022159SN/A MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) 4032680Sktlim@umich.edu { return actualTC->readMiscRegWithEffect(misc_reg, fault); } 4042SN/A 4052159SN/A Fault setMiscReg(int misc_reg, const MiscReg &val) 4062680Sktlim@umich.edu { return actualTC->setMiscReg(misc_reg, val); } 4072SN/A 4082159SN/A Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) 4092680Sktlim@umich.edu { return actualTC->setMiscRegWithEffect(misc_reg, val); } 4102190SN/A 4112190SN/A unsigned readStCondFailures() 4122680Sktlim@umich.edu { return actualTC->readStCondFailures(); } 4132190SN/A 4142190SN/A void setStCondFailures(unsigned sc_failures) 4152680Sktlim@umich.edu { actualTC->setStCondFailures(sc_failures); } 4161858SN/A#if FULL_SYSTEM 4172680Sktlim@umich.edu bool inPalMode() { return actualTC->inPalMode(); } 4182SN/A#endif 4192SN/A 4202190SN/A // @todo: Fix this! 4212680Sktlim@umich.edu bool misspeculating() { return actualTC->misspeculating(); } 4222190SN/A 4231858SN/A#if !FULL_SYSTEM 4242680Sktlim@umich.edu IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); } 425360SN/A 426360SN/A // used to shift args for indirect syscall 4272190SN/A void setSyscallArg(int i, IntReg val) 4282680Sktlim@umich.edu { actualTC->setSyscallArg(i, val); } 429360SN/A 4301450SN/A void setSyscallReturn(SyscallReturn return_value) 4312680Sktlim@umich.edu { actualTC->setSyscallReturn(return_value); } 432360SN/A 4332680Sktlim@umich.edu Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 4342SN/A#endif 4352525SN/A 4362525SN/A void changeRegFileContext(RegFile::ContextParam param, 4372525SN/A RegFile::ContextVal val) 4382525SN/A { 4392680Sktlim@umich.edu actualTC->changeRegFileContext(param, val); 4402525SN/A } 4412SN/A}; 4422SN/A 4432190SN/A#endif 444