thread_context.hh revision 2521
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __CPU_EXEC_CONTEXT_HH__ 30#define __CPU_EXEC_CONTEXT_HH__ 31 32#include "config/full_system.hh" 33#include "mem/request.hh" 34#include "sim/faults.hh" 35#include "sim/host.hh" 36#include "sim/serialize.hh" 37#include "sim/byteswap.hh" 38 39// @todo: Figure out a more architecture independent way to obtain the ITB and 40// DTB pointers. 41class AlphaDTB; 42class AlphaITB; 43class BaseCPU; 44class Event; 45class TranslatingPort; 46class FunctionalPort; 47class VirtualPort; 48class Process; 49class System; 50 51class ExecContext 52{ 53 protected: 54 typedef TheISA::RegFile RegFile; 55 typedef TheISA::MachInst MachInst; 56 typedef TheISA::IntReg IntReg; 57 typedef TheISA::FloatReg FloatReg; 58 typedef TheISA::FloatRegBits FloatRegBits; 59 typedef TheISA::MiscRegFile MiscRegFile; 60 typedef TheISA::MiscReg MiscReg; 61 public: 62 enum Status 63 { 64 /// Initialized but not running yet. All CPUs start in 65 /// this state, but most transition to Active on cycle 1. 66 /// In MP or SMT systems, non-primary contexts will stay 67 /// in this state until a thread is assigned to them. 68 Unallocated, 69 70 /// Running. Instructions should be executed only when 71 /// the context is in this state. 72 Active, 73 74 /// Temporarily inactive. Entered while waiting for 75 /// synchronization, etc. 76 Suspended, 77 78 /// Permanently shut down. Entered when target executes 79 /// m5exit pseudo-instruction. When all contexts enter 80 /// this state, the simulation will terminate. 81 Halted 82 }; 83 84 virtual ~ExecContext() { }; 85 86 virtual BaseCPU *getCpuPtr() = 0; 87 88 virtual void setCpuId(int id) = 0; 89 90 virtual int readCpuId() = 0; 91 92#if FULL_SYSTEM 93 virtual System *getSystemPtr() = 0; 94 95 virtual AlphaITB *getITBPtr() = 0; 96 97 virtual AlphaDTB * getDTBPtr() = 0; 98 99 virtual FunctionalPort *getPhysPort() = 0; 100 101 virtual VirtualPort *getVirtPort(ExecContext *xc = NULL) = 0; 102 103 virtual void delVirtPort(VirtualPort *vp) = 0; 104#else 105 virtual TranslatingPort *getMemPort() = 0; 106 107 virtual Process *getProcessPtr() = 0; 108#endif 109 110 virtual Status status() const = 0; 111 112 virtual void setStatus(Status new_status) = 0; 113 114 /// Set the status to Active. Optional delay indicates number of 115 /// cycles to wait before beginning execution. 116 virtual void activate(int delay = 1) = 0; 117 118 /// Set the status to Suspended. 119 virtual void suspend() = 0; 120 121 /// Set the status to Unallocated. 122 virtual void deallocate() = 0; 123 124 /// Set the status to Halted. 125 virtual void halt() = 0; 126 127#if FULL_SYSTEM 128 virtual void dumpFuncProfile() = 0; 129#endif 130 131 virtual void takeOverFrom(ExecContext *old_context) = 0; 132 133 virtual void regStats(const std::string &name) = 0; 134 135 virtual void serialize(std::ostream &os) = 0; 136 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 137 138#if FULL_SYSTEM 139 virtual Event *getQuiesceEvent() = 0; 140 141 // Not necessarily the best location for these... 142 // Having an extra function just to read these is obnoxious 143 virtual Tick readLastActivate() = 0; 144 virtual Tick readLastSuspend() = 0; 145 146 virtual void profileClear() = 0; 147 virtual void profileSample() = 0; 148#endif 149 150 virtual int getThreadNum() = 0; 151 152 virtual int getInstAsid() = 0; 153 virtual int getDataAsid() = 0; 154 155 virtual Fault translateInstReq(CpuRequestPtr &req) = 0; 156 157 virtual Fault translateDataReadReq(CpuRequestPtr &req) = 0; 158 159 virtual Fault translateDataWriteReq(CpuRequestPtr &req) = 0; 160 161 // Also somewhat obnoxious. Really only used for the TLB fault. 162 // However, may be quite useful in SPARC. 163 virtual TheISA::MachInst getInst() = 0; 164 165 virtual void copyArchRegs(ExecContext *xc) = 0; 166 167 virtual void clearArchRegs() = 0; 168 169 // 170 // New accessors for new decoder. 171 // 172 virtual uint64_t readIntReg(int reg_idx) = 0; 173 174 virtual FloatReg readFloatReg(int reg_idx, int width) = 0; 175 176 virtual FloatReg readFloatReg(int reg_idx) = 0; 177 178 virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0; 179 180 virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 181 182 virtual void setIntReg(int reg_idx, uint64_t val) = 0; 183 184 virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0; 185 186 virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 187 188 virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 189 190 virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0; 191 192 virtual uint64_t readPC() = 0; 193 194 virtual void setPC(uint64_t val) = 0; 195 196 virtual uint64_t readNextPC() = 0; 197 198 virtual void setNextPC(uint64_t val) = 0; 199 200 virtual uint64_t readNextNPC() = 0; 201 202 virtual void setNextNPC(uint64_t val) = 0; 203 204 virtual MiscReg readMiscReg(int misc_reg) = 0; 205 206 virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) = 0; 207 208 virtual Fault setMiscReg(int misc_reg, const MiscReg &val) = 0; 209 210 virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0; 211 212 // Also not necessarily the best location for these two. Hopefully will go 213 // away once we decide upon where st cond failures goes. 214 virtual unsigned readStCondFailures() = 0; 215 216 virtual void setStCondFailures(unsigned sc_failures) = 0; 217 218#if FULL_SYSTEM 219 virtual int readIntrFlag() = 0; 220 virtual void setIntrFlag(int val) = 0; 221 virtual Fault hwrei() = 0; 222 virtual bool inPalMode() = 0; 223 virtual bool simPalCheck(int palFunc) = 0; 224#endif 225 226 // Only really makes sense for old CPU model. Still could be useful though. 227 virtual bool misspeculating() = 0; 228 229#if !FULL_SYSTEM 230 virtual IntReg getSyscallArg(int i) = 0; 231 232 // used to shift args for indirect syscall 233 virtual void setSyscallArg(int i, IntReg val) = 0; 234 235 virtual void setSyscallReturn(SyscallReturn return_value) = 0; 236 237 virtual void syscall() = 0; 238 239 // Same with st cond failures. 240 virtual Counter readFuncExeInst() = 0; 241 242 virtual void setFuncExeInst(Counter new_val) = 0; 243#endif 244}; 245 246template <class XC> 247class ProxyExecContext : public ExecContext 248{ 249 public: 250 ProxyExecContext(XC *actual_xc) 251 { actualXC = actual_xc; } 252 253 private: 254 XC *actualXC; 255 256 public: 257 258 BaseCPU *getCpuPtr() { return actualXC->getCpuPtr(); } 259 260 void setCpuId(int id) { actualXC->setCpuId(id); } 261 262 int readCpuId() { return actualXC->readCpuId(); } 263 264#if FULL_SYSTEM 265 System *getSystemPtr() { return actualXC->getSystemPtr(); } 266 267 AlphaITB *getITBPtr() { return actualXC->getITBPtr(); } 268 269 AlphaDTB *getDTBPtr() { return actualXC->getDTBPtr(); } 270 271 FunctionalPort *getPhysPort() { return actualXC->getPhysPort(); } 272 273 VirtualPort *getVirtPort(ExecContext *xc = NULL) { return actualXC->getVirtPort(xc); } 274 275 void delVirtPort(VirtualPort *vp) { return actualXC->delVirtPort(vp); } 276#else 277 TranslatingPort *getMemPort() { return actualXC->getMemPort(); } 278 279 Process *getProcessPtr() { return actualXC->getProcessPtr(); } 280#endif 281 282 Status status() const { return actualXC->status(); } 283 284 void setStatus(Status new_status) { actualXC->setStatus(new_status); } 285 286 /// Set the status to Active. Optional delay indicates number of 287 /// cycles to wait before beginning execution. 288 void activate(int delay = 1) { actualXC->activate(delay); } 289 290 /// Set the status to Suspended. 291 void suspend() { actualXC->suspend(); } 292 293 /// Set the status to Unallocated. 294 void deallocate() { actualXC->deallocate(); } 295 296 /// Set the status to Halted. 297 void halt() { actualXC->halt(); } 298 299#if FULL_SYSTEM 300 void dumpFuncProfile() { actualXC->dumpFuncProfile(); } 301#endif 302 303 void takeOverFrom(ExecContext *oldContext) 304 { actualXC->takeOverFrom(oldContext); } 305 306 void regStats(const std::string &name) { actualXC->regStats(name); } 307 308 void serialize(std::ostream &os) { actualXC->serialize(os); } 309 void unserialize(Checkpoint *cp, const std::string §ion) 310 { actualXC->unserialize(cp, section); } 311 312#if FULL_SYSTEM 313 Event *getQuiesceEvent() { return actualXC->getQuiesceEvent(); } 314 315 Tick readLastActivate() { return actualXC->readLastActivate(); } 316 Tick readLastSuspend() { return actualXC->readLastSuspend(); } 317 318 void profileClear() { return actualXC->profileClear(); } 319 void profileSample() { return actualXC->profileSample(); } 320#endif 321 322 int getThreadNum() { return actualXC->getThreadNum(); } 323 324 int getInstAsid() { return actualXC->getInstAsid(); } 325 int getDataAsid() { return actualXC->getDataAsid(); } 326 327 Fault translateInstReq(CpuRequestPtr &req) 328 { return actualXC->translateInstReq(req); } 329 330 Fault translateDataReadReq(CpuRequestPtr &req) 331 { return actualXC->translateDataReadReq(req); } 332 333 Fault translateDataWriteReq(CpuRequestPtr &req) 334 { return actualXC->translateDataWriteReq(req); } 335 336 // @todo: Do I need this? 337 MachInst getInst() { return actualXC->getInst(); } 338 339 // @todo: Do I need this? 340 void copyArchRegs(ExecContext *xc) { actualXC->copyArchRegs(xc); } 341 342 void clearArchRegs() { actualXC->clearArchRegs(); } 343 344 // 345 // New accessors for new decoder. 346 // 347 uint64_t readIntReg(int reg_idx) 348 { return actualXC->readIntReg(reg_idx); } 349 350 FloatReg readFloatReg(int reg_idx, int width) 351 { return actualXC->readFloatReg(reg_idx, width); } 352 353 FloatReg readFloatReg(int reg_idx) 354 { return actualXC->readFloatReg(reg_idx); } 355 356 FloatRegBits readFloatRegBits(int reg_idx, int width) 357 { return actualXC->readFloatRegBits(reg_idx, width); } 358 359 FloatRegBits readFloatRegBits(int reg_idx) 360 { return actualXC->readFloatRegBits(reg_idx); } 361 362 void setIntReg(int reg_idx, uint64_t val) 363 { actualXC->setIntReg(reg_idx, val); } 364 365 void setFloatReg(int reg_idx, FloatReg val, int width) 366 { actualXC->setFloatReg(reg_idx, val, width); } 367 368 void setFloatReg(int reg_idx, FloatReg val) 369 { actualXC->setFloatReg(reg_idx, val); } 370 371 void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 372 { actualXC->setFloatRegBits(reg_idx, val, width); } 373 374 void setFloatRegBits(int reg_idx, FloatRegBits val) 375 { actualXC->setFloatRegBits(reg_idx, val); } 376 377 uint64_t readPC() { return actualXC->readPC(); } 378 379 void setPC(uint64_t val) { actualXC->setPC(val); } 380 381 uint64_t readNextPC() { return actualXC->readNextPC(); } 382 383 void setNextPC(uint64_t val) { actualXC->setNextPC(val); } 384 385 uint64_t readNextNPC() { return actualXC->readNextNPC(); } 386 387 void setNextNPC(uint64_t val) { actualXC->setNextNPC(val); } 388 389 MiscReg readMiscReg(int misc_reg) 390 { return actualXC->readMiscReg(misc_reg); } 391 392 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) 393 { return actualXC->readMiscRegWithEffect(misc_reg, fault); } 394 395 Fault setMiscReg(int misc_reg, const MiscReg &val) 396 { return actualXC->setMiscReg(misc_reg, val); } 397 398 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) 399 { return actualXC->setMiscRegWithEffect(misc_reg, val); } 400 401 unsigned readStCondFailures() 402 { return actualXC->readStCondFailures(); } 403 404 void setStCondFailures(unsigned sc_failures) 405 { actualXC->setStCondFailures(sc_failures); } 406 407#if FULL_SYSTEM 408 int readIntrFlag() { return actualXC->readIntrFlag(); } 409 410 void setIntrFlag(int val) { actualXC->setIntrFlag(val); } 411 412 Fault hwrei() { return actualXC->hwrei(); } 413 414 bool inPalMode() { return actualXC->inPalMode(); } 415 416 bool simPalCheck(int palFunc) { return actualXC->simPalCheck(palFunc); } 417#endif 418 419 // @todo: Fix this! 420 bool misspeculating() { return actualXC->misspeculating(); } 421 422#if !FULL_SYSTEM 423 IntReg getSyscallArg(int i) { return actualXC->getSyscallArg(i); } 424 425 // used to shift args for indirect syscall 426 void setSyscallArg(int i, IntReg val) 427 { actualXC->setSyscallArg(i, val); } 428 429 void setSyscallReturn(SyscallReturn return_value) 430 { actualXC->setSyscallReturn(return_value); } 431 432 void syscall() { actualXC->syscall(); } 433 434 Counter readFuncExeInst() { return actualXC->readFuncExeInst(); } 435 436 void setFuncExeInst(Counter new_val) 437 { return actualXC->setFuncExeInst(new_val); } 438#endif 439}; 440 441#endif 442