thread_context.hh revision 2455
17138Sgblack@eecs.umich.edu/* 27138Sgblack@eecs.umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 37138Sgblack@eecs.umich.edu * All rights reserved. 47138Sgblack@eecs.umich.edu * 57138Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 67138Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 77138Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 87138Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 97138Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 107138Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 117138Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 127138Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 137138Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 147138Sgblack@eecs.umich.edu * this software without specific prior written permission. 157138Sgblack@eecs.umich.edu * 167138Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177138Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187138Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197138Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207138Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217138Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 227138Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237138Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 247138Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 257138Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 267138Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 277138Sgblack@eecs.umich.edu */ 287138Sgblack@eecs.umich.edu 297138Sgblack@eecs.umich.edu#ifndef __CPU_EXEC_CONTEXT_HH__ 307138Sgblack@eecs.umich.edu#define __CPU_EXEC_CONTEXT_HH__ 317138Sgblack@eecs.umich.edu 327138Sgblack@eecs.umich.edu#include "config/full_system.hh" 337138Sgblack@eecs.umich.edu#include "mem/request.hh" 347138Sgblack@eecs.umich.edu#include "sim/faults.hh" 357138Sgblack@eecs.umich.edu#include "sim/host.hh" 367138Sgblack@eecs.umich.edu#include "sim/serialize.hh" 377138Sgblack@eecs.umich.edu#include "sim/byteswap.hh" 387138Sgblack@eecs.umich.edu 397138Sgblack@eecs.umich.edu// forward declaration: see functional_memory.hh 407138Sgblack@eecs.umich.edu// @todo: Figure out a more architecture independent way to obtain the ITB and 417138Sgblack@eecs.umich.edu// DTB pointers. 427138Sgblack@eecs.umich.educlass AlphaDTB; 437138Sgblack@eecs.umich.educlass AlphaITB; 447138Sgblack@eecs.umich.educlass BaseCPU; 457138Sgblack@eecs.umich.educlass Event; 467138Sgblack@eecs.umich.educlass PhysicalMemory; 477138Sgblack@eecs.umich.educlass TranslatingPort; 487138Sgblack@eecs.umich.educlass Process; 497138Sgblack@eecs.umich.educlass System; 507138Sgblack@eecs.umich.edu 517138Sgblack@eecs.umich.educlass ExecContext 527138Sgblack@eecs.umich.edu{ 537138Sgblack@eecs.umich.edu protected: 547138Sgblack@eecs.umich.edu typedef TheISA::RegFile RegFile; 557138Sgblack@eecs.umich.edu typedef TheISA::MachInst MachInst; 567138Sgblack@eecs.umich.edu typedef TheISA::IntReg IntReg; 577138Sgblack@eecs.umich.edu typedef TheISA::FloatReg FloatReg; 587138Sgblack@eecs.umich.edu typedef TheISA::FloatRegBits FloatRegBits; 597138Sgblack@eecs.umich.edu typedef TheISA::MiscRegFile MiscRegFile; 607138Sgblack@eecs.umich.edu typedef TheISA::MiscReg MiscReg; 617138Sgblack@eecs.umich.edu public: 627138Sgblack@eecs.umich.edu enum Status 637138Sgblack@eecs.umich.edu { 647138Sgblack@eecs.umich.edu /// Initialized but not running yet. All CPUs start in 657138Sgblack@eecs.umich.edu /// this state, but most transition to Active on cycle 1. 667138Sgblack@eecs.umich.edu /// In MP or SMT systems, non-primary contexts will stay 677138Sgblack@eecs.umich.edu /// in this state until a thread is assigned to them. 687138Sgblack@eecs.umich.edu Unallocated, 697138Sgblack@eecs.umich.edu 707138Sgblack@eecs.umich.edu /// Running. Instructions should be executed only when 717138Sgblack@eecs.umich.edu /// the context is in this state. 727138Sgblack@eecs.umich.edu Active, 737138Sgblack@eecs.umich.edu 747138Sgblack@eecs.umich.edu /// Temporarily inactive. Entered while waiting for 757138Sgblack@eecs.umich.edu /// synchronization, etc. 767138Sgblack@eecs.umich.edu Suspended, 777138Sgblack@eecs.umich.edu 787138Sgblack@eecs.umich.edu /// Permanently shut down. Entered when target executes 797138Sgblack@eecs.umich.edu /// m5exit pseudo-instruction. When all contexts enter 807138Sgblack@eecs.umich.edu /// this state, the simulation will terminate. 817138Sgblack@eecs.umich.edu Halted 827138Sgblack@eecs.umich.edu }; 837138Sgblack@eecs.umich.edu 847138Sgblack@eecs.umich.edu virtual ~ExecContext() { }; 857138Sgblack@eecs.umich.edu 867138Sgblack@eecs.umich.edu virtual TranslatingPort *getMemPort() = 0; 877138Sgblack@eecs.umich.edu 887138Sgblack@eecs.umich.edu virtual BaseCPU *getCpuPtr() = 0; 897138Sgblack@eecs.umich.edu 907138Sgblack@eecs.umich.edu virtual void setCpuId(int id) = 0; 917138Sgblack@eecs.umich.edu 927138Sgblack@eecs.umich.edu virtual int readCpuId() = 0; 937138Sgblack@eecs.umich.edu 947138Sgblack@eecs.umich.edu#if FULL_SYSTEM 957138Sgblack@eecs.umich.edu virtual System *getSystemPtr() = 0; 967138Sgblack@eecs.umich.edu 977138Sgblack@eecs.umich.edu virtual PhysicalMemory *getPhysMemPtr() = 0; 987138Sgblack@eecs.umich.edu 997181Sgblack@eecs.umich.edu virtual AlphaITB *getITBPtr() = 0; 1007138Sgblack@eecs.umich.edu 1017188Sgblack@eecs.umich.edu virtual AlphaDTB * getDTBPtr() = 0; 1027188Sgblack@eecs.umich.edu#else 1037138Sgblack@eecs.umich.edu virtual Process *getProcessPtr() = 0; 1047138Sgblack@eecs.umich.edu#endif 1057138Sgblack@eecs.umich.edu 1067138Sgblack@eecs.umich.edu virtual Status status() const = 0; 1077138Sgblack@eecs.umich.edu 1087138Sgblack@eecs.umich.edu virtual void setStatus(Status new_status) = 0; 1097184Sgblack@eecs.umich.edu 1107138Sgblack@eecs.umich.edu /// Set the status to Active. Optional delay indicates number of 1117138Sgblack@eecs.umich.edu /// cycles to wait before beginning execution. 1127138Sgblack@eecs.umich.edu virtual void activate(int delay = 1) = 0; 1137138Sgblack@eecs.umich.edu 1147138Sgblack@eecs.umich.edu /// Set the status to Suspended. 1157138Sgblack@eecs.umich.edu virtual void suspend() = 0; 1167184Sgblack@eecs.umich.edu 1177188Sgblack@eecs.umich.edu /// Set the status to Unallocated. 1187184Sgblack@eecs.umich.edu virtual void deallocate() = 0; 1197184Sgblack@eecs.umich.edu 1207188Sgblack@eecs.umich.edu /// Set the status to Halted. 1217184Sgblack@eecs.umich.edu virtual void halt() = 0; 1227184Sgblack@eecs.umich.edu 1237184Sgblack@eecs.umich.edu#if FULL_SYSTEM 1247184Sgblack@eecs.umich.edu virtual void dumpFuncProfile() = 0; 1257188Sgblack@eecs.umich.edu#endif 1267188Sgblack@eecs.umich.edu 1277188Sgblack@eecs.umich.edu virtual void takeOverFrom(ExecContext *old_context) = 0; 1287188Sgblack@eecs.umich.edu 1297188Sgblack@eecs.umich.edu virtual void regStats(const std::string &name) = 0; 1307188Sgblack@eecs.umich.edu 1317188Sgblack@eecs.umich.edu virtual void serialize(std::ostream &os) = 0; 1327188Sgblack@eecs.umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 1337188Sgblack@eecs.umich.edu 1347188Sgblack@eecs.umich.edu#if FULL_SYSTEM 1357188Sgblack@eecs.umich.edu virtual Event *getQuiesceEvent() = 0; 1367188Sgblack@eecs.umich.edu 1377184Sgblack@eecs.umich.edu // Not necessarily the best location for these... 1387184Sgblack@eecs.umich.edu // Having an extra function just to read these is obnoxious 1397184Sgblack@eecs.umich.edu virtual Tick readLastActivate() = 0; 1407184Sgblack@eecs.umich.edu virtual Tick readLastSuspend() = 0; 1417184Sgblack@eecs.umich.edu 1427184Sgblack@eecs.umich.edu virtual void profileClear() = 0; 1437184Sgblack@eecs.umich.edu virtual void profileSample() = 0; 1447184Sgblack@eecs.umich.edu#endif 1457138Sgblack@eecs.umich.edu 1467138Sgblack@eecs.umich.edu virtual int getThreadNum() = 0; 1477138Sgblack@eecs.umich.edu 1487138Sgblack@eecs.umich.edu virtual int getInstAsid() = 0; 1497138Sgblack@eecs.umich.edu virtual int getDataAsid() = 0; 1507184Sgblack@eecs.umich.edu 1517188Sgblack@eecs.umich.edu virtual Fault translateInstReq(CpuRequestPtr &req) = 0; 1527184Sgblack@eecs.umich.edu 1537184Sgblack@eecs.umich.edu virtual Fault translateDataReadReq(CpuRequestPtr &req) = 0; 1547188Sgblack@eecs.umich.edu 1557184Sgblack@eecs.umich.edu virtual Fault translateDataWriteReq(CpuRequestPtr &req) = 0; 1567184Sgblack@eecs.umich.edu 1577184Sgblack@eecs.umich.edu // Also somewhat obnoxious. Really only used for the TLB fault. 1587184Sgblack@eecs.umich.edu // However, may be quite useful in SPARC. 1597188Sgblack@eecs.umich.edu virtual TheISA::MachInst getInst() = 0; 1607188Sgblack@eecs.umich.edu 1617188Sgblack@eecs.umich.edu virtual void copyArchRegs(ExecContext *xc) = 0; 1627188Sgblack@eecs.umich.edu 1637188Sgblack@eecs.umich.edu virtual void clearArchRegs() = 0; 1647188Sgblack@eecs.umich.edu 1657188Sgblack@eecs.umich.edu // 1667188Sgblack@eecs.umich.edu // New accessors for new decoder. 1677188Sgblack@eecs.umich.edu // 1687188Sgblack@eecs.umich.edu virtual uint64_t readIntReg(int reg_idx) = 0; 1697188Sgblack@eecs.umich.edu 1707188Sgblack@eecs.umich.edu virtual FloatReg readFloatReg(int reg_idx, int width) = 0; 1717184Sgblack@eecs.umich.edu 1727184Sgblack@eecs.umich.edu virtual FloatReg readFloatReg(int reg_idx) = 0; 1737184Sgblack@eecs.umich.edu 1747184Sgblack@eecs.umich.edu virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0; 1757184Sgblack@eecs.umich.edu 1767184Sgblack@eecs.umich.edu virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 1777184Sgblack@eecs.umich.edu 1787184Sgblack@eecs.umich.edu virtual void setIntReg(int reg_idx, uint64_t val) = 0; 1797138Sgblack@eecs.umich.edu 1807138Sgblack@eecs.umich.edu virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0; 1817138Sgblack@eecs.umich.edu 1827138Sgblack@eecs.umich.edu virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 1837138Sgblack@eecs.umich.edu 1847138Sgblack@eecs.umich.edu virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 1857188Sgblack@eecs.umich.edu 1867138Sgblack@eecs.umich.edu virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0; 1877138Sgblack@eecs.umich.edu 1887138Sgblack@eecs.umich.edu virtual uint64_t readPC() = 0; 1897138Sgblack@eecs.umich.edu 1907188Sgblack@eecs.umich.edu virtual void setPC(uint64_t val) = 0; 1917138Sgblack@eecs.umich.edu 1927138Sgblack@eecs.umich.edu virtual uint64_t readNextPC() = 0; 1937138Sgblack@eecs.umich.edu 1947138Sgblack@eecs.umich.edu virtual void setNextPC(uint64_t val) = 0; 1957188Sgblack@eecs.umich.edu 1967188Sgblack@eecs.umich.edu virtual uint64_t readNextNPC() = 0; 1977188Sgblack@eecs.umich.edu 1987188Sgblack@eecs.umich.edu virtual void setNextNPC(uint64_t val) = 0; 1997188Sgblack@eecs.umich.edu 2007184Sgblack@eecs.umich.edu virtual MiscReg readMiscReg(int misc_reg) = 0; 2017188Sgblack@eecs.umich.edu 2027188Sgblack@eecs.umich.edu virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) = 0; 2037188Sgblack@eecs.umich.edu 2047188Sgblack@eecs.umich.edu virtual Fault setMiscReg(int misc_reg, const MiscReg &val) = 0; 2057188Sgblack@eecs.umich.edu 2067188Sgblack@eecs.umich.edu virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0; 2077188Sgblack@eecs.umich.edu 2087188Sgblack@eecs.umich.edu // Also not necessarily the best location for these two. Hopefully will go 2097188Sgblack@eecs.umich.edu // away once we decide upon where st cond failures goes. 2107188Sgblack@eecs.umich.edu virtual unsigned readStCondFailures() = 0; 2117188Sgblack@eecs.umich.edu 2127188Sgblack@eecs.umich.edu virtual void setStCondFailures(unsigned sc_failures) = 0; 2137188Sgblack@eecs.umich.edu 2147188Sgblack@eecs.umich.edu#if FULL_SYSTEM 2157188Sgblack@eecs.umich.edu virtual int readIntrFlag() = 0; 2167188Sgblack@eecs.umich.edu virtual void setIntrFlag(int val) = 0; 2177188Sgblack@eecs.umich.edu virtual Fault hwrei() = 0; 2187188Sgblack@eecs.umich.edu virtual bool inPalMode() = 0; 2197188Sgblack@eecs.umich.edu virtual bool simPalCheck(int palFunc) = 0; 2207188Sgblack@eecs.umich.edu#endif 2217188Sgblack@eecs.umich.edu 2227188Sgblack@eecs.umich.edu // Only really makes sense for old CPU model. Still could be useful though. 2237188Sgblack@eecs.umich.edu virtual bool misspeculating() = 0; 2247188Sgblack@eecs.umich.edu 2257188Sgblack@eecs.umich.edu#if !FULL_SYSTEM 2267188Sgblack@eecs.umich.edu virtual IntReg getSyscallArg(int i) = 0; 2277188Sgblack@eecs.umich.edu 2287188Sgblack@eecs.umich.edu // used to shift args for indirect syscall 2297188Sgblack@eecs.umich.edu virtual void setSyscallArg(int i, IntReg val) = 0; 2307188Sgblack@eecs.umich.edu 2317188Sgblack@eecs.umich.edu virtual void setSyscallReturn(SyscallReturn return_value) = 0; 2327188Sgblack@eecs.umich.edu 2337188Sgblack@eecs.umich.edu virtual void syscall() = 0; 2347185Sgblack@eecs.umich.edu 2357188Sgblack@eecs.umich.edu // Same with st cond failures. 2367185Sgblack@eecs.umich.edu virtual Counter readFuncExeInst() = 0; 2377185Sgblack@eecs.umich.edu 2387188Sgblack@eecs.umich.edu virtual void setFuncExeInst(Counter new_val) = 0; 2397188Sgblack@eecs.umich.edu#endif 2407188Sgblack@eecs.umich.edu}; 2417188Sgblack@eecs.umich.edu 2427188Sgblack@eecs.umich.edutemplate <class XC> 2437188Sgblack@eecs.umich.educlass ProxyExecContext : public ExecContext 2447188Sgblack@eecs.umich.edu{ 2457188Sgblack@eecs.umich.edu public: 2467188Sgblack@eecs.umich.edu ProxyExecContext(XC *actual_xc) 2477188Sgblack@eecs.umich.edu { actualXC = actual_xc; } 2487188Sgblack@eecs.umich.edu 2497188Sgblack@eecs.umich.edu private: 2507156Sgblack@eecs.umich.edu XC *actualXC; 2517188Sgblack@eecs.umich.edu 2527188Sgblack@eecs.umich.edu public: 2537138Sgblack@eecs.umich.edu 254 TranslatingPort *getMemPort() { return actualXC->getMemPort(); } 255 256 BaseCPU *getCpuPtr() { return actualXC->getCpuPtr(); } 257 258 void setCpuId(int id) { actualXC->setCpuId(id); } 259 260 int readCpuId() { return actualXC->readCpuId(); } 261 262#if FULL_SYSTEM 263 System *getSystemPtr() { return actualXC->getSystemPtr(); } 264 265 PhysicalMemory *getPhysMemPtr() { return actualXC->getPhysMemPtr(); } 266 267 AlphaITB *getITBPtr() { return actualXC->getITBPtr(); } 268 269 AlphaDTB *getDTBPtr() { return actualXC->getDTBPtr(); } 270#else 271 Process *getProcessPtr() { return actualXC->getProcessPtr(); } 272#endif 273 274 Status status() const { return actualXC->status(); } 275 276 void setStatus(Status new_status) { actualXC->setStatus(new_status); } 277 278 /// Set the status to Active. Optional delay indicates number of 279 /// cycles to wait before beginning execution. 280 void activate(int delay = 1) { actualXC->activate(delay); } 281 282 /// Set the status to Suspended. 283 void suspend() { actualXC->suspend(); } 284 285 /// Set the status to Unallocated. 286 void deallocate() { actualXC->deallocate(); } 287 288 /// Set the status to Halted. 289 void halt() { actualXC->halt(); } 290 291#if FULL_SYSTEM 292 void dumpFuncProfile() { actualXC->dumpFuncProfile(); } 293#endif 294 295 void takeOverFrom(ExecContext *oldContext) 296 { actualXC->takeOverFrom(oldContext); } 297 298 void regStats(const std::string &name) { actualXC->regStats(name); } 299 300 void serialize(std::ostream &os) { actualXC->serialize(os); } 301 void unserialize(Checkpoint *cp, const std::string §ion) 302 { actualXC->unserialize(cp, section); } 303 304#if FULL_SYSTEM 305 Event *getQuiesceEvent() { return actualXC->getQuiesceEvent(); } 306 307 Tick readLastActivate() { return actualXC->readLastActivate(); } 308 Tick readLastSuspend() { return actualXC->readLastSuspend(); } 309 310 void profileClear() { return actualXC->profileClear(); } 311 void profileSample() { return actualXC->profileSample(); } 312#endif 313 314 int getThreadNum() { return actualXC->getThreadNum(); } 315 316 int getInstAsid() { return actualXC->getInstAsid(); } 317 int getDataAsid() { return actualXC->getDataAsid(); } 318 319 Fault translateInstReq(CpuRequestPtr &req) 320 { return actualXC->translateInstReq(req); } 321 322 Fault translateDataReadReq(CpuRequestPtr &req) 323 { return actualXC->translateDataReadReq(req); } 324 325 Fault translateDataWriteReq(CpuRequestPtr &req) 326 { return actualXC->translateDataWriteReq(req); } 327 328 // @todo: Do I need this? 329 MachInst getInst() { return actualXC->getInst(); } 330 331 // @todo: Do I need this? 332 void copyArchRegs(ExecContext *xc) { actualXC->copyArchRegs(xc); } 333 334 void clearArchRegs() { actualXC->clearArchRegs(); } 335 336 // 337 // New accessors for new decoder. 338 // 339 uint64_t readIntReg(int reg_idx) 340 { return actualXC->readIntReg(reg_idx); } 341 342 FloatReg readFloatReg(int reg_idx, int width) 343 { return actualXC->readFloatReg(reg_idx, width); } 344 345 FloatReg readFloatReg(int reg_idx) 346 { return actualXC->readFloatReg(reg_idx); } 347 348 FloatRegBits readFloatRegBits(int reg_idx, int width) 349 { return actualXC->readFloatRegBits(reg_idx, width); } 350 351 FloatRegBits readFloatRegBits(int reg_idx) 352 { return actualXC->readFloatRegBits(reg_idx); } 353 354 void setIntReg(int reg_idx, uint64_t val) 355 { actualXC->setIntReg(reg_idx, val); } 356 357 void setFloatReg(int reg_idx, FloatReg val, int width) 358 { actualXC->setFloatReg(reg_idx, val, width); } 359 360 void setFloatReg(int reg_idx, FloatReg val) 361 { actualXC->setFloatReg(reg_idx, val); } 362 363 void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 364 { actualXC->setFloatRegBits(reg_idx, val, width); } 365 366 void setFloatRegBits(int reg_idx, FloatRegBits val) 367 { actualXC->setFloatRegBits(reg_idx, val); } 368 369 uint64_t readPC() { return actualXC->readPC(); } 370 371 void setPC(uint64_t val) { actualXC->setPC(val); } 372 373 uint64_t readNextPC() { return actualXC->readNextPC(); } 374 375 void setNextPC(uint64_t val) { actualXC->setNextPC(val); } 376 377 uint64_t readNextNPC() { return actualXC->readNextNPC(); } 378 379 void setNextNPC(uint64_t val) { actualXC->setNextNPC(val); } 380 381 MiscReg readMiscReg(int misc_reg) 382 { return actualXC->readMiscReg(misc_reg); } 383 384 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) 385 { return actualXC->readMiscRegWithEffect(misc_reg, fault); } 386 387 Fault setMiscReg(int misc_reg, const MiscReg &val) 388 { return actualXC->setMiscReg(misc_reg, val); } 389 390 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) 391 { return actualXC->setMiscRegWithEffect(misc_reg, val); } 392 393 unsigned readStCondFailures() 394 { return actualXC->readStCondFailures(); } 395 396 void setStCondFailures(unsigned sc_failures) 397 { actualXC->setStCondFailures(sc_failures); } 398 399#if FULL_SYSTEM 400 int readIntrFlag() { return actualXC->readIntrFlag(); } 401 402 void setIntrFlag(int val) { actualXC->setIntrFlag(val); } 403 404 Fault hwrei() { return actualXC->hwrei(); } 405 406 bool inPalMode() { return actualXC->inPalMode(); } 407 408 bool simPalCheck(int palFunc) { return actualXC->simPalCheck(palFunc); } 409#endif 410 411 // @todo: Fix this! 412 bool misspeculating() { return actualXC->misspeculating(); } 413 414#if !FULL_SYSTEM 415 IntReg getSyscallArg(int i) { return actualXC->getSyscallArg(i); } 416 417 // used to shift args for indirect syscall 418 void setSyscallArg(int i, IntReg val) 419 { actualXC->setSyscallArg(i, val); } 420 421 void setSyscallReturn(SyscallReturn return_value) 422 { actualXC->setSyscallReturn(return_value); } 423 424 void syscall() { actualXC->syscall(); } 425 426 Counter readFuncExeInst() { return actualXC->readFuncExeInst(); } 427 428 void setFuncExeInst(Counter new_val) 429 { return actualXC->setFuncExeInst(new_val); } 430#endif 431}; 432 433#endif 434