thread_context.hh revision 217
112542Sgiacomo.travaglini@arm.com/* 27139Sgblack@eecs.umich.edu * Copyright (c) 2003 The Regents of The University of Michigan 37139Sgblack@eecs.umich.edu * All rights reserved. 47139Sgblack@eecs.umich.edu * 57139Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 67139Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 77139Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 87139Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 97139Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 107139Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 117139Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 127139Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 137139Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 147139Sgblack@eecs.umich.edu * this software without specific prior written permission. 157139Sgblack@eecs.umich.edu * 167139Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177139Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187139Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197139Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207139Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217139Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 227139Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237139Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 247139Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 257139Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 267139Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 277139Sgblack@eecs.umich.edu */ 287139Sgblack@eecs.umich.edu 297139Sgblack@eecs.umich.edu#ifndef __EXEC_CONTEXT_HH__ 307139Sgblack@eecs.umich.edu#define __EXEC_CONTEXT_HH__ 317139Sgblack@eecs.umich.edu 327139Sgblack@eecs.umich.edu#include "sim/host.hh" 337139Sgblack@eecs.umich.edu#include "mem/mem_req.hh" 347139Sgblack@eecs.umich.edu#include "sim/serialize.hh" 357139Sgblack@eecs.umich.edu 367139Sgblack@eecs.umich.edu// forward declaration: see functional_memory.hh 377139Sgblack@eecs.umich.educlass FunctionalMemory; 387255Sgblack@eecs.umich.educlass PhysicalMemory; 397243Sgblack@eecs.umich.educlass BaseCPU; 407243Sgblack@eecs.umich.edu 417255Sgblack@eecs.umich.edu#ifdef FULL_SYSTEM 427255Sgblack@eecs.umich.edu 437243Sgblack@eecs.umich.edu#include "targetarch/alpha_memory.hh" 447243Sgblack@eecs.umich.educlass MemoryController; 457255Sgblack@eecs.umich.edu 467255Sgblack@eecs.umich.edu#include "kern/tru64/kernel_stats.hh" 477255Sgblack@eecs.umich.edu#include "sim/system.hh" 487255Sgblack@eecs.umich.edu 497255Sgblack@eecs.umich.edu#else // !FULL_SYSTEM 507255Sgblack@eecs.umich.edu 517255Sgblack@eecs.umich.edu#include "sim/prog.hh" 527255Sgblack@eecs.umich.edu 537255Sgblack@eecs.umich.edu#endif // FULL_SYSTEM 547255Sgblack@eecs.umich.edu 557255Sgblack@eecs.umich.edu// 567256Sgblack@eecs.umich.edu// The ExecContext object represents a functional context for 577256Sgblack@eecs.umich.edu// instruction execution. It incorporates everything required for 587255Sgblack@eecs.umich.edu// architecture-level functional simulation of a single thread. 597256Sgblack@eecs.umich.edu// 607255Sgblack@eecs.umich.edu 617256Sgblack@eecs.umich.educlass ExecContext 627255Sgblack@eecs.umich.edu{ 637255Sgblack@eecs.umich.edu public: 647258Sgblack@eecs.umich.edu enum Status { Unallocated, Active, Suspended, Halted }; 657258Sgblack@eecs.umich.edu 667255Sgblack@eecs.umich.edu private: 677258Sgblack@eecs.umich.edu Status _status; 687255Sgblack@eecs.umich.edu 697258Sgblack@eecs.umich.edu public: 707255Sgblack@eecs.umich.edu Status status() const { return _status; } 717243Sgblack@eecs.umich.edu 727255Sgblack@eecs.umich.edu void setStatus(Status new_status); 737243Sgblack@eecs.umich.edu 747243Sgblack@eecs.umich.edu#ifdef FULL_SYSTEM 757243Sgblack@eecs.umich.edu public: 767243Sgblack@eecs.umich.edu KernelStats kernelStats; 777139Sgblack@eecs.umich.edu#endif 787188Sgblack@eecs.umich.edu 797188Sgblack@eecs.umich.edu public: 807188Sgblack@eecs.umich.edu RegFile regs; // correct-path register context 817188Sgblack@eecs.umich.edu 827188Sgblack@eecs.umich.edu // pointer to CPU associated with this context 837139Sgblack@eecs.umich.edu BaseCPU *cpu; 847139Sgblack@eecs.umich.edu 857139Sgblack@eecs.umich.edu // Index of hardware thread context on the CPU that this represents. 867139Sgblack@eecs.umich.edu int thread_num; 877188Sgblack@eecs.umich.edu 887188Sgblack@eecs.umich.edu // ID of this context w.r.t. the System or Process object to which 897188Sgblack@eecs.umich.edu // it belongs. For full-system mode, this is the system CPU ID. 907188Sgblack@eecs.umich.edu int cpu_id; 917188Sgblack@eecs.umich.edu 927188Sgblack@eecs.umich.edu#ifdef FULL_SYSTEM 937139Sgblack@eecs.umich.edu 947146Sgblack@eecs.umich.edu FunctionalMemory *mem; 957141Sgblack@eecs.umich.edu AlphaItb *itb; 967139Sgblack@eecs.umich.edu AlphaDtb *dtb; 977139Sgblack@eecs.umich.edu System *system; 987139Sgblack@eecs.umich.edu 997146Sgblack@eecs.umich.edu // the following two fields are redundant, since we can always 1007141Sgblack@eecs.umich.edu // look them up through the system pointer, but we'll leave them 1017139Sgblack@eecs.umich.edu // here for now for convenience 1027146Sgblack@eecs.umich.edu MemoryController *memCtrl; 1037141Sgblack@eecs.umich.edu PhysicalMemory *physmem; 1047139Sgblack@eecs.umich.edu 1057139Sgblack@eecs.umich.edu#else 1067139Sgblack@eecs.umich.edu Process *process; 1077139Sgblack@eecs.umich.edu 1087139Sgblack@eecs.umich.edu FunctionalMemory *mem; // functional storage for process address space 1097188Sgblack@eecs.umich.edu 1107188Sgblack@eecs.umich.edu // Address space ID. Note that this is used for TIMING cache 1117188Sgblack@eecs.umich.edu // simulation only; all functional memory accesses should use 1127188Sgblack@eecs.umich.edu // one of the FunctionalMemory pointers above. 1137188Sgblack@eecs.umich.edu short asid; 1147188Sgblack@eecs.umich.edu 1157188Sgblack@eecs.umich.edu#endif 1167188Sgblack@eecs.umich.edu 1177188Sgblack@eecs.umich.edu 1187188Sgblack@eecs.umich.edu /* 1197188Sgblack@eecs.umich.edu * number of executed instructions, for matching with syscall trace 1207188Sgblack@eecs.umich.edu * points in EIO files. 1217188Sgblack@eecs.umich.edu */ 1227188Sgblack@eecs.umich.edu Counter func_exe_insn; 1237188Sgblack@eecs.umich.edu 1247188Sgblack@eecs.umich.edu // 1257188Sgblack@eecs.umich.edu // Count failed store conditionals so we can warn of apparent 1267188Sgblack@eecs.umich.edu // application deadlock situations. 1277188Sgblack@eecs.umich.edu unsigned storeCondFailures; 1287188Sgblack@eecs.umich.edu 1297139Sgblack@eecs.umich.edu // constructor: initialize context from given process structure 1307139Sgblack@eecs.umich.edu#ifdef FULL_SYSTEM 1317139Sgblack@eecs.umich.edu ExecContext(BaseCPU *_cpu, int _thread_num, System *_system, 1327139Sgblack@eecs.umich.edu AlphaItb *_itb, AlphaDtb *_dtb, FunctionalMemory *_dem); 1337139Sgblack@eecs.umich.edu#else 1347139Sgblack@eecs.umich.edu ExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid); 1357139Sgblack@eecs.umich.edu ExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem, 1367139Sgblack@eecs.umich.edu int _asid); 1377139Sgblack@eecs.umich.edu#endif 1387139Sgblack@eecs.umich.edu virtual ~ExecContext() {} 1397139Sgblack@eecs.umich.edu 1407139Sgblack@eecs.umich.edu virtual void takeOverFrom(ExecContext *oldContext); 1417139Sgblack@eecs.umich.edu 1427139Sgblack@eecs.umich.edu void regStats(const std::string &name); 1437139Sgblack@eecs.umich.edu 1447139Sgblack@eecs.umich.edu void serialize(std::ostream &os); 1457139Sgblack@eecs.umich.edu void unserialize(IniFile &db, const std::string §ion); 1467139Sgblack@eecs.umich.edu 1477139Sgblack@eecs.umich.edu#ifdef FULL_SYSTEM 1487139Sgblack@eecs.umich.edu bool validInstAddr(Addr addr) { return true; } 1497139Sgblack@eecs.umich.edu bool validDataAddr(Addr addr) { return true; } 1507188Sgblack@eecs.umich.edu int getInstAsid() { return ITB_ASN_ASN(regs.ipr[TheISA::IPR_ITB_ASN]); } 1517188Sgblack@eecs.umich.edu int getDataAsid() { return DTB_ASN_ASN(regs.ipr[TheISA::IPR_DTB_ASN]); } 1527188Sgblack@eecs.umich.edu 1537188Sgblack@eecs.umich.edu Fault translateInstReq(MemReqPtr req) 1547139Sgblack@eecs.umich.edu { 1557188Sgblack@eecs.umich.edu return itb->translate(req); 1567139Sgblack@eecs.umich.edu } 1577188Sgblack@eecs.umich.edu 1587139Sgblack@eecs.umich.edu Fault translateDataReadReq(MemReqPtr req) 1597139Sgblack@eecs.umich.edu { 1607139Sgblack@eecs.umich.edu return dtb->translate(req, false); 1617139Sgblack@eecs.umich.edu } 1627139Sgblack@eecs.umich.edu 1637139Sgblack@eecs.umich.edu Fault translateDataWriteReq(MemReqPtr req) 1647139Sgblack@eecs.umich.edu { 1657139Sgblack@eecs.umich.edu return dtb->translate(req, true); 1667210Sgblack@eecs.umich.edu } 1677210Sgblack@eecs.umich.edu 1687210Sgblack@eecs.umich.edu#else 1697210Sgblack@eecs.umich.edu bool validInstAddr(Addr addr) 1707210Sgblack@eecs.umich.edu { return process->validInstAddr(addr); } 1717210Sgblack@eecs.umich.edu 1727210Sgblack@eecs.umich.edu bool validDataAddr(Addr addr) 1737227Sgblack@eecs.umich.edu { return process->validDataAddr(addr); } 1747227Sgblack@eecs.umich.edu 1757227Sgblack@eecs.umich.edu int getInstAsid() { return asid; } 1767227Sgblack@eecs.umich.edu int getDataAsid() { return asid; } 1777227Sgblack@eecs.umich.edu 1787227Sgblack@eecs.umich.edu Fault dummyTranslation(MemReqPtr req) 1797227Sgblack@eecs.umich.edu { 1807227Sgblack@eecs.umich.edu#if 0 1817210Sgblack@eecs.umich.edu assert((req->vaddr >> 48 & 0xffff) == 0); 1827237Sgblack@eecs.umich.edu#endif 1837237Sgblack@eecs.umich.edu 1847237Sgblack@eecs.umich.edu // put the asid in the upper 16 bits of the paddr 1857237Sgblack@eecs.umich.edu req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16); 1867237Sgblack@eecs.umich.edu req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16; 1877237Sgblack@eecs.umich.edu return No_Fault; 1887237Sgblack@eecs.umich.edu } 1897210Sgblack@eecs.umich.edu Fault translateInstReq(MemReqPtr req) 1907227Sgblack@eecs.umich.edu { 1917210Sgblack@eecs.umich.edu return dummyTranslation(req); 1927227Sgblack@eecs.umich.edu } 1937210Sgblack@eecs.umich.edu Fault translateDataReadReq(MemReqPtr req) 1947210Sgblack@eecs.umich.edu { 1957210Sgblack@eecs.umich.edu return dummyTranslation(req); 1967210Sgblack@eecs.umich.edu } 1977210Sgblack@eecs.umich.edu Fault translateDataWriteReq(MemReqPtr req) 1987240Sgblack@eecs.umich.edu { 1997235Sgblack@eecs.umich.edu return dummyTranslation(req); 2007235Sgblack@eecs.umich.edu } 2017235Sgblack@eecs.umich.edu 2027235Sgblack@eecs.umich.edu#endif 2037235Sgblack@eecs.umich.edu 2047235Sgblack@eecs.umich.edu template <class T> 2057240Sgblack@eecs.umich.edu Fault read(MemReqPtr req, T& data) 2067240Sgblack@eecs.umich.edu { 2077240Sgblack@eecs.umich.edu#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM) 2087240Sgblack@eecs.umich.edu if (req->flags & LOCKED) { 2097240Sgblack@eecs.umich.edu MiscRegFile *cregs = &req->xc->regs.miscRegs; 2107240Sgblack@eecs.umich.edu cregs->lock_addr = req->paddr; 2117240Sgblack@eecs.umich.edu cregs->lock_flag = true; 2127240Sgblack@eecs.umich.edu } 2137240Sgblack@eecs.umich.edu#endif 2147240Sgblack@eecs.umich.edu return mem->read(req, data); 2157210Sgblack@eecs.umich.edu } 2167210Sgblack@eecs.umich.edu 2177210Sgblack@eecs.umich.edu template <class T> 2187210Sgblack@eecs.umich.edu Fault write(MemReqPtr req, T& data) 2197210Sgblack@eecs.umich.edu { 2207227Sgblack@eecs.umich.edu#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM) 2217227Sgblack@eecs.umich.edu 2227227Sgblack@eecs.umich.edu MiscRegFile *cregs; 2237227Sgblack@eecs.umich.edu 2247227Sgblack@eecs.umich.edu // If this is a store conditional, act appropriately 2257227Sgblack@eecs.umich.edu if (req->flags & LOCKED) { 2267210Sgblack@eecs.umich.edu cregs = &req->xc->regs.miscRegs; 2277235Sgblack@eecs.umich.edu 2287235Sgblack@eecs.umich.edu if (req->flags & UNCACHEABLE) { 2297235Sgblack@eecs.umich.edu // Don't update result register (see stq_c in isa_desc) 2307235Sgblack@eecs.umich.edu req->result = 2; 2317235Sgblack@eecs.umich.edu req->xc->storeCondFailures = 0;//Needed? [RGD] 2327235Sgblack@eecs.umich.edu } else { 2337235Sgblack@eecs.umich.edu req->result = cregs->lock_flag; 2347235Sgblack@eecs.umich.edu if (!cregs->lock_flag || 2357210Sgblack@eecs.umich.edu ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) { 2367235Sgblack@eecs.umich.edu cregs->lock_flag = false; 2377210Sgblack@eecs.umich.edu if (((++req->xc->storeCondFailures) % 100000) == 0) { 2387235Sgblack@eecs.umich.edu std::cerr << "Warning: " 2397210Sgblack@eecs.umich.edu << req->xc->storeCondFailures 2407210Sgblack@eecs.umich.edu << " consecutive store conditional failures " 2417210Sgblack@eecs.umich.edu << "on cpu " << req->xc->cpu_id 2427210Sgblack@eecs.umich.edu << std::endl; 2437210Sgblack@eecs.umich.edu } 2447211Sgblack@eecs.umich.edu return No_Fault; 2457211Sgblack@eecs.umich.edu } 2467211Sgblack@eecs.umich.edu else req->xc->storeCondFailures = 0; 2477210Sgblack@eecs.umich.edu } 2487235Sgblack@eecs.umich.edu } 2497235Sgblack@eecs.umich.edu 2507235Sgblack@eecs.umich.edu // Need to clear any locked flags on other proccessors for 2517235Sgblack@eecs.umich.edu // this address. Only do this for succsful Store Conditionals 2527235Sgblack@eecs.umich.edu // and all other stores (WH64?). Unsuccessful Store 2537235Sgblack@eecs.umich.edu // Conditionals would have returned above, and wouldn't fall 2547235Sgblack@eecs.umich.edu // through. 2557235Sgblack@eecs.umich.edu for (int i = 0; i < system->execContexts.size(); i++){ 2567210Sgblack@eecs.umich.edu cregs = &system->execContexts[i]->regs.miscRegs; 2577235Sgblack@eecs.umich.edu if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) { 2587210Sgblack@eecs.umich.edu cregs->lock_flag = false; 2597235Sgblack@eecs.umich.edu } 2607210Sgblack@eecs.umich.edu } 2617210Sgblack@eecs.umich.edu 2627211Sgblack@eecs.umich.edu#endif 2637211Sgblack@eecs.umich.edu return mem->write(req, data); 2647211Sgblack@eecs.umich.edu } 2657210Sgblack@eecs.umich.edu 2667210Sgblack@eecs.umich.edu virtual bool misspeculating(); 2677210Sgblack@eecs.umich.edu 2687210Sgblack@eecs.umich.edu 2697235Sgblack@eecs.umich.edu // 2707235Sgblack@eecs.umich.edu // New accessors for new decoder. 2717235Sgblack@eecs.umich.edu // 2727235Sgblack@eecs.umich.edu uint64_t readIntReg(int reg_idx) 2737235Sgblack@eecs.umich.edu { 2747235Sgblack@eecs.umich.edu return regs.intRegFile[reg_idx]; 2757235Sgblack@eecs.umich.edu } 2767235Sgblack@eecs.umich.edu 2777210Sgblack@eecs.umich.edu float readFloatRegSingle(int reg_idx) 2787235Sgblack@eecs.umich.edu { 2797210Sgblack@eecs.umich.edu return (float)regs.floatRegFile.d[reg_idx]; 2807235Sgblack@eecs.umich.edu } 2817210Sgblack@eecs.umich.edu 2827210Sgblack@eecs.umich.edu double readFloatRegDouble(int reg_idx) 2837210Sgblack@eecs.umich.edu { 2847210Sgblack@eecs.umich.edu return regs.floatRegFile.d[reg_idx]; 2857210Sgblack@eecs.umich.edu } 2867227Sgblack@eecs.umich.edu 2877227Sgblack@eecs.umich.edu uint64_t readFloatRegInt(int reg_idx) 2887227Sgblack@eecs.umich.edu { 2897227Sgblack@eecs.umich.edu return regs.floatRegFile.q[reg_idx]; 2907227Sgblack@eecs.umich.edu } 2917227Sgblack@eecs.umich.edu 2927210Sgblack@eecs.umich.edu void setIntReg(int reg_idx, uint64_t val) 2937235Sgblack@eecs.umich.edu { 2947235Sgblack@eecs.umich.edu regs.intRegFile[reg_idx] = val; 2957235Sgblack@eecs.umich.edu } 2967235Sgblack@eecs.umich.edu 2977235Sgblack@eecs.umich.edu void setFloatRegSingle(int reg_idx, float val) 2987235Sgblack@eecs.umich.edu { 2997235Sgblack@eecs.umich.edu regs.floatRegFile.d[reg_idx] = (double)val; 3007235Sgblack@eecs.umich.edu } 3017210Sgblack@eecs.umich.edu 3027235Sgblack@eecs.umich.edu void setFloatRegDouble(int reg_idx, double val) 3037210Sgblack@eecs.umich.edu { 3047235Sgblack@eecs.umich.edu regs.floatRegFile.d[reg_idx] = val; 3057210Sgblack@eecs.umich.edu } 3067210Sgblack@eecs.umich.edu 3077210Sgblack@eecs.umich.edu void setFloatRegInt(int reg_idx, uint64_t val) 3087210Sgblack@eecs.umich.edu { 3097250Sgblack@eecs.umich.edu regs.floatRegFile.q[reg_idx] = val; 3107235Sgblack@eecs.umich.edu } 3117235Sgblack@eecs.umich.edu 3127235Sgblack@eecs.umich.edu uint64_t readPC() 3137235Sgblack@eecs.umich.edu { 3147235Sgblack@eecs.umich.edu return regs.pc; 3157235Sgblack@eecs.umich.edu } 3167250Sgblack@eecs.umich.edu 3177250Sgblack@eecs.umich.edu void setNextPC(uint64_t val) 3187250Sgblack@eecs.umich.edu { 3197250Sgblack@eecs.umich.edu regs.npc = val; 3207250Sgblack@eecs.umich.edu } 3217250Sgblack@eecs.umich.edu 3227250Sgblack@eecs.umich.edu uint64_t readUniq() 3237250Sgblack@eecs.umich.edu { 3247250Sgblack@eecs.umich.edu return regs.miscRegs.uniq; 3257250Sgblack@eecs.umich.edu } 3267250Sgblack@eecs.umich.edu 3277250Sgblack@eecs.umich.edu void setUniq(uint64_t val) 3287210Sgblack@eecs.umich.edu { 3297210Sgblack@eecs.umich.edu regs.miscRegs.uniq = val; 3307210Sgblack@eecs.umich.edu } 3317210Sgblack@eecs.umich.edu 3327210Sgblack@eecs.umich.edu uint64_t readFpcr() 3337210Sgblack@eecs.umich.edu { 3347210Sgblack@eecs.umich.edu return regs.miscRegs.fpcr; 3357210Sgblack@eecs.umich.edu } 3367210Sgblack@eecs.umich.edu 3377194Sgblack@eecs.umich.edu void setFpcr(uint64_t val) 3387194Sgblack@eecs.umich.edu { 3397194Sgblack@eecs.umich.edu regs.miscRegs.fpcr = val; 3407194Sgblack@eecs.umich.edu } 3417194Sgblack@eecs.umich.edu 3427194Sgblack@eecs.umich.edu#ifdef FULL_SYSTEM 3437194Sgblack@eecs.umich.edu uint64_t readIpr(int idx, Fault &fault); 3447194Sgblack@eecs.umich.edu Fault setIpr(int idx, uint64_t val); 3457194Sgblack@eecs.umich.edu Fault hwrei(); 3467194Sgblack@eecs.umich.edu void ev5_trap(Fault fault); 3477194Sgblack@eecs.umich.edu bool simPalCheck(int palFunc); 3487194Sgblack@eecs.umich.edu#endif 3497194Sgblack@eecs.umich.edu 3507216Sgblack@eecs.umich.edu#ifndef FULL_SYSTEM 3517194Sgblack@eecs.umich.edu void syscall() 3527224Sgblack@eecs.umich.edu { 3537194Sgblack@eecs.umich.edu process->syscall(this); 3547224Sgblack@eecs.umich.edu } 3557194Sgblack@eecs.umich.edu#endif 3567218Sgblack@eecs.umich.edu}; 3577194Sgblack@eecs.umich.edu 3587216Sgblack@eecs.umich.edu 3597194Sgblack@eecs.umich.edu// for non-speculative execution context, spec_mode is always false 3607218Sgblack@eecs.umich.eduinline bool 3617194Sgblack@eecs.umich.eduExecContext::misspeculating() 3627194Sgblack@eecs.umich.edu{ 3637194Sgblack@eecs.umich.edu return false; 3647194Sgblack@eecs.umich.edu} 3657194Sgblack@eecs.umich.edu 3667194Sgblack@eecs.umich.edu#endif // __EXEC_CONTEXT_HH__ 3677194Sgblack@eecs.umich.edu