thread_context.hh revision 13622
12SN/A/* 213610Sgiacomo.gabrielli@arm.com * Copyright (c) 2011-2012, 2016-2018 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152190SN/A * Copyright (c) 2006 The Regents of The University of Michigan 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665SN/A * 412665SN/A * Authors: Kevin Lim 422SN/A */ 432SN/A 442680Sktlim@umich.edu#ifndef __CPU_THREAD_CONTEXT_HH__ 452680Sktlim@umich.edu#define __CPU_THREAD_CONTEXT_HH__ 462SN/A 478229Snate@binkert.org#include <iostream> 487680Sgblack@eecs.umich.edu#include <string> 497680Sgblack@eecs.umich.edu 506329Sgblack@eecs.umich.edu#include "arch/registers.hh" 513453Sgblack@eecs.umich.edu#include "arch/types.hh" 526216Snate@binkert.org#include "base/types.hh" 536658Snate@binkert.org#include "config/the_isa.hh" 5412104Snathanael.premillieu@arm.com#include "cpu/reg_class.hh" 552SN/A 562190SN/A// @todo: Figure out a more architecture independent way to obtain the ITB and 572190SN/A// DTB pointers. 583453Sgblack@eecs.umich.edunamespace TheISA 593453Sgblack@eecs.umich.edu{ 609020Sgblack@eecs.umich.edu class Decoder; 613453Sgblack@eecs.umich.edu} 622190SN/Aclass BaseCPU; 6312406Sgabeblack@google.comclass BaseTLB; 648887Sgeoffrey.blake@arm.comclass CheckerCPU; 657680Sgblack@eecs.umich.educlass Checkpoint; 662313SN/Aclass EndQuiesceEvent; 678706Sandreas.hansson@arm.comclass SETranslatingPortProxy; 688706Sandreas.hansson@arm.comclass FSTranslatingPortProxy; 698706Sandreas.hansson@arm.comclass PortProxy; 702190SN/Aclass Process; 712190SN/Aclass System; 723548Sgblack@eecs.umich.edunamespace TheISA { 733548Sgblack@eecs.umich.edu namespace Kernel { 743548Sgblack@eecs.umich.edu class Statistics; 758902Sandreas.hansson@arm.com } 768902Sandreas.hansson@arm.com} 772SN/A 782680Sktlim@umich.edu/** 792680Sktlim@umich.edu * ThreadContext is the external interface to all thread state for 802680Sktlim@umich.edu * anything outside of the CPU. It provides all accessor methods to 812680Sktlim@umich.edu * state that might be needed by external objects, ranging from 822680Sktlim@umich.edu * register values to things such as kernel stats. It is an abstract 832680Sktlim@umich.edu * base class; the CPU can create its own ThreadContext by either 842680Sktlim@umich.edu * deriving from it, or using the templated ProxyThreadContext. 852680Sktlim@umich.edu * 862680Sktlim@umich.edu * The ThreadContext is slightly different than the ExecContext. The 872680Sktlim@umich.edu * ThreadContext provides access to an individual thread's state; an 882680Sktlim@umich.edu * ExecContext provides ISA access to the CPU (meaning it is 892682Sktlim@umich.edu * implicitly multithreaded on SMT systems). Additionally the 902680Sktlim@umich.edu * ThreadState is an abstract class that exactly defines the 912680Sktlim@umich.edu * interface; the ExecContext is a more implicit interface that must 922680Sktlim@umich.edu * be implemented so that the ISA can access whatever state it needs. 932680Sktlim@umich.edu */ 942680Sktlim@umich.educlass ThreadContext 952SN/A{ 962107SN/A protected: 972107SN/A typedef TheISA::MachInst MachInst; 9812109SRekai.GonzalezAlberquilla@arm.com using VecRegContainer = TheISA::VecRegContainer; 9912109SRekai.GonzalezAlberquilla@arm.com using VecElem = TheISA::VecElem; 10013610Sgiacomo.gabrielli@arm.com using VecPredRegContainer = TheISA::VecPredRegContainer; 10113610Sgiacomo.gabrielli@arm.com 1022SN/A public: 1036029Ssteve.reinhardt@amd.com 104246SN/A enum Status 105246SN/A { 106246SN/A /// Running. Instructions should be executed only when 107246SN/A /// the context is in this state. 108246SN/A Active, 109246SN/A 110246SN/A /// Temporarily inactive. Entered while waiting for 1112190SN/A /// synchronization, etc. 112246SN/A Suspended, 113246SN/A 114246SN/A /// Permanently shut down. Entered when target executes 115246SN/A /// m5exit pseudo-instruction. When all contexts enter 116246SN/A /// this state, the simulation will terminate. 117246SN/A Halted 118246SN/A }; 1192SN/A 1202680Sktlim@umich.edu virtual ~ThreadContext() { }; 1212423SN/A 1222190SN/A virtual BaseCPU *getCpuPtr() = 0; 123180SN/A 12410110Sandreas.hansson@arm.com virtual int cpuId() const = 0; 1252190SN/A 12610190Sakash.bagdia@arm.com virtual uint32_t socketId() const = 0; 12710190Sakash.bagdia@arm.com 12810110Sandreas.hansson@arm.com virtual int threadId() const = 0; 1295715Shsul@eecs.umich.edu 1305715Shsul@eecs.umich.edu virtual void setThreadId(int id) = 0; 1315714Shsul@eecs.umich.edu 13210110Sandreas.hansson@arm.com virtual int contextId() const = 0; 1335714Shsul@eecs.umich.edu 1345714Shsul@eecs.umich.edu virtual void setContextId(int id) = 0; 1355714Shsul@eecs.umich.edu 13612406Sgabeblack@google.com virtual BaseTLB *getITBPtr() = 0; 1372190SN/A 13812406Sgabeblack@google.com virtual BaseTLB *getDTBPtr() = 0; 1392521SN/A 1408887Sgeoffrey.blake@arm.com virtual CheckerCPU *getCheckerCpuPtr() = 0; 1418733Sgeoffrey.blake@arm.com 1429020Sgblack@eecs.umich.edu virtual TheISA::Decoder *getDecoderPtr() = 0; 1438541Sgblack@eecs.umich.edu 1444997Sgblack@eecs.umich.edu virtual System *getSystemPtr() = 0; 1454997Sgblack@eecs.umich.edu 1463548Sgblack@eecs.umich.edu virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 1472654SN/A 1488852Sandreas.hansson@arm.com virtual PortProxy &getPhysProxy() = 0; 1492521SN/A 1508852Sandreas.hansson@arm.com virtual FSTranslatingPortProxy &getVirtProxy() = 0; 1513673Srdreslin@umich.edu 1528706Sandreas.hansson@arm.com /** 1538706Sandreas.hansson@arm.com * Initialise the physical and virtual port proxies and tie them to 1548706Sandreas.hansson@arm.com * the data port of the CPU. 1558706Sandreas.hansson@arm.com * 1568706Sandreas.hansson@arm.com * tc ThreadContext for the virtual-to-physical translation 1578706Sandreas.hansson@arm.com */ 1588706Sandreas.hansson@arm.com virtual void initMemProxies(ThreadContext *tc) = 0; 1598799Sgblack@eecs.umich.edu 1608852Sandreas.hansson@arm.com virtual SETranslatingPortProxy &getMemProxy() = 0; 1612518SN/A 1622190SN/A virtual Process *getProcessPtr() = 0; 1632190SN/A 16411886Sbrandon.potter@amd.com virtual void setProcessPtr(Process *p) = 0; 16511886Sbrandon.potter@amd.com 1662190SN/A virtual Status status() const = 0; 1672159SN/A 1682235SN/A virtual void setStatus(Status new_status) = 0; 1692103SN/A 17010407Smitch.hayenga@arm.com /// Set the status to Active. 17110407Smitch.hayenga@arm.com virtual void activate() = 0; 172393SN/A 173393SN/A /// Set the status to Suspended. 17410407Smitch.hayenga@arm.com virtual void suspend() = 0; 175393SN/A 176393SN/A /// Set the status to Halted. 17710407Smitch.hayenga@arm.com virtual void halt() = 0; 1782159SN/A 17911627Smichael.lebeane@amd.com /// Quiesce thread context 18011627Smichael.lebeane@amd.com void quiesce(); 18111627Smichael.lebeane@amd.com 18211627Smichael.lebeane@amd.com /// Quiesce, suspend, and schedule activate at resume 18311627Smichael.lebeane@amd.com void quiesceTick(Tick resume); 18411627Smichael.lebeane@amd.com 1852190SN/A virtual void dumpFuncProfile() = 0; 1862159SN/A 1872680Sktlim@umich.edu virtual void takeOverFrom(ThreadContext *old_context) = 0; 1882159SN/A 1892190SN/A virtual void regStats(const std::string &name) = 0; 1902159SN/A 1912313SN/A virtual EndQuiesceEvent *getQuiesceEvent() = 0; 1922235SN/A 1932235SN/A // Not necessarily the best location for these... 1942235SN/A // Having an extra function just to read these is obnoxious 1952235SN/A virtual Tick readLastActivate() = 0; 1962235SN/A virtual Tick readLastSuspend() = 0; 1972254SN/A 1982254SN/A virtual void profileClear() = 0; 1992254SN/A virtual void profileSample() = 0; 2002235SN/A 2012680Sktlim@umich.edu virtual void copyArchRegs(ThreadContext *tc) = 0; 2022159SN/A 2032190SN/A virtual void clearArchRegs() = 0; 2042159SN/A 2052159SN/A // 2062159SN/A // New accessors for new decoder. 2072159SN/A // 20813557Sgabeblack@google.com virtual RegVal readIntReg(int reg_idx) = 0; 2092159SN/A 21013611Sgabeblack@google.com virtual RegVal readFloatReg(int reg_idx) = 0; 2112159SN/A 21212109SRekai.GonzalezAlberquilla@arm.com virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0; 21312109SRekai.GonzalezAlberquilla@arm.com virtual VecRegContainer& getWritableVecReg(const RegId& reg) = 0; 21412109SRekai.GonzalezAlberquilla@arm.com 21512109SRekai.GonzalezAlberquilla@arm.com /** Vector Register Lane Interfaces. */ 21612109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 21712109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 8bit operand. */ 21812109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane8 21912109SRekai.GonzalezAlberquilla@arm.com readVec8BitLaneReg(const RegId& reg) const = 0; 22012109SRekai.GonzalezAlberquilla@arm.com 22112109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 16bit operand. */ 22212109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane16 22312109SRekai.GonzalezAlberquilla@arm.com readVec16BitLaneReg(const RegId& reg) const = 0; 22412109SRekai.GonzalezAlberquilla@arm.com 22512109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 32bit operand. */ 22612109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane32 22712109SRekai.GonzalezAlberquilla@arm.com readVec32BitLaneReg(const RegId& reg) const = 0; 22812109SRekai.GonzalezAlberquilla@arm.com 22912109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 64bit operand. */ 23012109SRekai.GonzalezAlberquilla@arm.com virtual ConstVecLane64 23112109SRekai.GonzalezAlberquilla@arm.com readVec64BitLaneReg(const RegId& reg) const = 0; 23212109SRekai.GonzalezAlberquilla@arm.com 23312109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector register. */ 23412109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 23512109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::Byte>& val) = 0; 23612109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 23712109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::TwoByte>& val) = 0; 23812109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 23912109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::FourByte>& val) = 0; 24012109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 24112109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::EightByte>& val) = 0; 24212109SRekai.GonzalezAlberquilla@arm.com /** @} */ 24312109SRekai.GonzalezAlberquilla@arm.com 24412109SRekai.GonzalezAlberquilla@arm.com virtual const VecElem& readVecElem(const RegId& reg) const = 0; 24512109SRekai.GonzalezAlberquilla@arm.com 24613610Sgiacomo.gabrielli@arm.com virtual const VecPredRegContainer& readVecPredReg(const RegId& reg) 24713610Sgiacomo.gabrielli@arm.com const = 0; 24813610Sgiacomo.gabrielli@arm.com virtual VecPredRegContainer& getWritableVecPredReg(const RegId& reg) = 0; 24913610Sgiacomo.gabrielli@arm.com 25013622Sgabeblack@google.com virtual RegVal readCCReg(int reg_idx) = 0; 2519920Syasuko.eckert@amd.com 25213557Sgabeblack@google.com virtual void setIntReg(int reg_idx, RegVal val) = 0; 2532159SN/A 25413611Sgabeblack@google.com virtual void setFloatReg(int reg_idx, RegVal val) = 0; 2552455SN/A 25612109SRekai.GonzalezAlberquilla@arm.com virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0; 25712109SRekai.GonzalezAlberquilla@arm.com 25812109SRekai.GonzalezAlberquilla@arm.com virtual void setVecElem(const RegId& reg, const VecElem& val) = 0; 25912109SRekai.GonzalezAlberquilla@arm.com 26013610Sgiacomo.gabrielli@arm.com virtual void setVecPredReg(const RegId& reg, 26113610Sgiacomo.gabrielli@arm.com const VecPredRegContainer& val) = 0; 26213610Sgiacomo.gabrielli@arm.com 26313622Sgabeblack@google.com virtual void setCCReg(int reg_idx, RegVal val) = 0; 2649920Syasuko.eckert@amd.com 2657720Sgblack@eecs.umich.edu virtual TheISA::PCState pcState() = 0; 2662159SN/A 2677720Sgblack@eecs.umich.edu virtual void pcState(const TheISA::PCState &val) = 0; 2682159SN/A 26911886Sbrandon.potter@amd.com void 27011886Sbrandon.potter@amd.com setNPC(Addr val) 27111886Sbrandon.potter@amd.com { 27211886Sbrandon.potter@amd.com TheISA::PCState pc_state = pcState(); 27311886Sbrandon.potter@amd.com pc_state.setNPC(val); 27411886Sbrandon.potter@amd.com pcState(pc_state); 27511886Sbrandon.potter@amd.com } 27611886Sbrandon.potter@amd.com 2778733Sgeoffrey.blake@arm.com virtual void pcStateNoRecord(const TheISA::PCState &val) = 0; 2788733Sgeoffrey.blake@arm.com 2797720Sgblack@eecs.umich.edu virtual Addr instAddr() = 0; 2802159SN/A 2817720Sgblack@eecs.umich.edu virtual Addr nextInstAddr() = 0; 2822159SN/A 2837720Sgblack@eecs.umich.edu virtual MicroPC microPC() = 0; 2845260Sksewell@umich.edu 28513557Sgabeblack@google.com virtual RegVal readMiscRegNoEffect(int misc_reg) const = 0; 2864172Ssaidi@eecs.umich.edu 28713557Sgabeblack@google.com virtual RegVal readMiscReg(int misc_reg) = 0; 2882159SN/A 28913582Sgabeblack@google.com virtual void setMiscRegNoEffect(int misc_reg, RegVal val) = 0; 2902190SN/A 29113582Sgabeblack@google.com virtual void setMiscReg(int misc_reg, RegVal val) = 0; 2922190SN/A 29312106SRekai.GonzalezAlberquilla@arm.com virtual RegId flattenRegId(const RegId& regId) const = 0; 2946313Sgblack@eecs.umich.edu 29513557Sgabeblack@google.com virtual RegVal 29612106SRekai.GonzalezAlberquilla@arm.com readRegOtherThread(const RegId& misc_reg, ThreadID tid) 2976221Snate@binkert.org { 2986221Snate@binkert.org return 0; 2996221Snate@binkert.org } 3004661Sksewell@umich.edu 3016221Snate@binkert.org virtual void 30213582Sgabeblack@google.com setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid) 3036221Snate@binkert.org { 3046221Snate@binkert.org } 3054661Sksewell@umich.edu 3062235SN/A // Also not necessarily the best location for these two. Hopefully will go 3072235SN/A // away once we decide upon where st cond failures goes. 3082190SN/A virtual unsigned readStCondFailures() = 0; 3092190SN/A 3102190SN/A virtual void setStCondFailures(unsigned sc_failures) = 0; 3112159SN/A 3122235SN/A // Same with st cond failures. 3132190SN/A virtual Counter readFuncExeInst() = 0; 3142834Sksewell@umich.edu 31511877Sbrandon.potter@amd.com virtual void syscall(int64_t callnum, Fault *fault) = 0; 3164111Sgblack@eecs.umich.edu 3172834Sksewell@umich.edu // This function exits the thread context in the CPU and returns 3182834Sksewell@umich.edu // 1 if the CPU has no more active threads (meaning it's OK to exit); 3192834Sksewell@umich.edu // Used in syscall-emulation mode when a thread calls the exit syscall. 3202834Sksewell@umich.edu virtual int exit() { return 1; }; 3212525SN/A 3225217Ssaidi@eecs.umich.edu /** function to compare two thread contexts (for debugging) */ 3235217Ssaidi@eecs.umich.edu static void compare(ThreadContext *one, ThreadContext *two); 3249426SAndreas.Sandberg@ARM.com 3259426SAndreas.Sandberg@ARM.com /** @{ */ 3269426SAndreas.Sandberg@ARM.com /** 3279426SAndreas.Sandberg@ARM.com * Flat register interfaces 3289426SAndreas.Sandberg@ARM.com * 3299426SAndreas.Sandberg@ARM.com * Some architectures have different registers visible in 3309426SAndreas.Sandberg@ARM.com * different modes. Such architectures "flatten" a register (see 33112106SRekai.GonzalezAlberquilla@arm.com * flattenRegId()) to map it into the 3329426SAndreas.Sandberg@ARM.com * gem5 register file. This interface provides a flat interface to 3339426SAndreas.Sandberg@ARM.com * the underlying register file, which allows for example 3349426SAndreas.Sandberg@ARM.com * serialization code to access all registers. 3359426SAndreas.Sandberg@ARM.com */ 3369426SAndreas.Sandberg@ARM.com 33713557Sgabeblack@google.com virtual RegVal readIntRegFlat(int idx) = 0; 33813557Sgabeblack@google.com virtual void setIntRegFlat(int idx, RegVal val) = 0; 3399426SAndreas.Sandberg@ARM.com 34013611Sgabeblack@google.com virtual RegVal readFloatRegFlat(int idx) = 0; 34113611Sgabeblack@google.com virtual void setFloatRegFlat(int idx, RegVal val) = 0; 3429426SAndreas.Sandberg@ARM.com 34312109SRekai.GonzalezAlberquilla@arm.com virtual const VecRegContainer& readVecRegFlat(int idx) const = 0; 34412109SRekai.GonzalezAlberquilla@arm.com virtual VecRegContainer& getWritableVecRegFlat(int idx) = 0; 34512109SRekai.GonzalezAlberquilla@arm.com virtual void setVecRegFlat(int idx, const VecRegContainer& val) = 0; 34612109SRekai.GonzalezAlberquilla@arm.com 34712109SRekai.GonzalezAlberquilla@arm.com virtual const VecElem& readVecElemFlat(const RegIndex& idx, 34812109SRekai.GonzalezAlberquilla@arm.com const ElemIndex& elemIdx) const = 0; 34912109SRekai.GonzalezAlberquilla@arm.com virtual void setVecElemFlat(const RegIndex& idx, const ElemIndex& elemIdx, 35012109SRekai.GonzalezAlberquilla@arm.com const VecElem& val) = 0; 35112109SRekai.GonzalezAlberquilla@arm.com 35213610Sgiacomo.gabrielli@arm.com virtual const VecPredRegContainer& readVecPredRegFlat(int idx) const = 0; 35313610Sgiacomo.gabrielli@arm.com virtual VecPredRegContainer& getWritableVecPredRegFlat(int idx) = 0; 35413610Sgiacomo.gabrielli@arm.com virtual void setVecPredRegFlat(int idx, 35513610Sgiacomo.gabrielli@arm.com const VecPredRegContainer& val) = 0; 35613610Sgiacomo.gabrielli@arm.com 35713622Sgabeblack@google.com virtual RegVal readCCRegFlat(int idx) = 0; 35813622Sgabeblack@google.com virtual void setCCRegFlat(int idx, RegVal val) = 0; 3599426SAndreas.Sandberg@ARM.com /** @} */ 3609426SAndreas.Sandberg@ARM.com 3612159SN/A}; 3622159SN/A 3632682Sktlim@umich.edu/** 3642682Sktlim@umich.edu * ProxyThreadContext class that provides a way to implement a 3652682Sktlim@umich.edu * ThreadContext without having to derive from it. ThreadContext is an 3662682Sktlim@umich.edu * abstract class, so anything that derives from it and uses its 3672682Sktlim@umich.edu * interface will pay the overhead of virtual function calls. This 3682682Sktlim@umich.edu * class is created to enable a user-defined Thread object to be used 3692682Sktlim@umich.edu * wherever ThreadContexts are used, without paying the overhead of 3702682Sktlim@umich.edu * virtual function calls when it is used by itself. See 3712682Sktlim@umich.edu * simple_thread.hh for an example of this. 3722682Sktlim@umich.edu */ 3732680Sktlim@umich.edutemplate <class TC> 3742680Sktlim@umich.educlass ProxyThreadContext : public ThreadContext 3752190SN/A{ 3762190SN/A public: 3772680Sktlim@umich.edu ProxyThreadContext(TC *actual_tc) 3782680Sktlim@umich.edu { actualTC = actual_tc; } 3792159SN/A 3802190SN/A private: 3812680Sktlim@umich.edu TC *actualTC; 3822SN/A 3832SN/A public: 3842SN/A 3852680Sktlim@umich.edu BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 3862SN/A 38710110Sandreas.hansson@arm.com int cpuId() const { return actualTC->cpuId(); } 3882SN/A 38910190Sakash.bagdia@arm.com uint32_t socketId() const { return actualTC->socketId(); } 39010190Sakash.bagdia@arm.com 39110110Sandreas.hansson@arm.com int threadId() const { return actualTC->threadId(); } 3925715Shsul@eecs.umich.edu 39310110Sandreas.hansson@arm.com void setThreadId(int id) { actualTC->setThreadId(id); } 3945714Shsul@eecs.umich.edu 39510110Sandreas.hansson@arm.com int contextId() const { return actualTC->contextId(); } 3965714Shsul@eecs.umich.edu 3975714Shsul@eecs.umich.edu void setContextId(int id) { actualTC->setContextId(id); } 3985714Shsul@eecs.umich.edu 39912406Sgabeblack@google.com BaseTLB *getITBPtr() { return actualTC->getITBPtr(); } 4001917SN/A 40112406Sgabeblack@google.com BaseTLB *getDTBPtr() { return actualTC->getDTBPtr(); } 4022521SN/A 4038887Sgeoffrey.blake@arm.com CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); } 4048733Sgeoffrey.blake@arm.com 4059020Sgblack@eecs.umich.edu TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); } 4068541Sgblack@eecs.umich.edu 4074997Sgblack@eecs.umich.edu System *getSystemPtr() { return actualTC->getSystemPtr(); } 4084997Sgblack@eecs.umich.edu 4093548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *getKernelStats() 4103548Sgblack@eecs.umich.edu { return actualTC->getKernelStats(); } 4112654SN/A 4128852Sandreas.hansson@arm.com PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); } 4132521SN/A 4148852Sandreas.hansson@arm.com FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); } 4153673Srdreslin@umich.edu 4168706Sandreas.hansson@arm.com void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); } 4178799Sgblack@eecs.umich.edu 4188852Sandreas.hansson@arm.com SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); } 4192518SN/A 4202680Sktlim@umich.edu Process *getProcessPtr() { return actualTC->getProcessPtr(); } 4212SN/A 42211886Sbrandon.potter@amd.com void setProcessPtr(Process *p) { actualTC->setProcessPtr(p); } 42311886Sbrandon.potter@amd.com 4242680Sktlim@umich.edu Status status() const { return actualTC->status(); } 425595SN/A 4262680Sktlim@umich.edu void setStatus(Status new_status) { actualTC->setStatus(new_status); } 4272SN/A 42810407Smitch.hayenga@arm.com /// Set the status to Active. 42910407Smitch.hayenga@arm.com void activate() { actualTC->activate(); } 4302SN/A 4312190SN/A /// Set the status to Suspended. 43210407Smitch.hayenga@arm.com void suspend() { actualTC->suspend(); } 4332SN/A 4342190SN/A /// Set the status to Halted. 43510407Smitch.hayenga@arm.com void halt() { actualTC->halt(); } 436217SN/A 43711627Smichael.lebeane@amd.com /// Quiesce thread context 43811627Smichael.lebeane@amd.com void quiesce() { actualTC->quiesce(); } 43911627Smichael.lebeane@amd.com 44011627Smichael.lebeane@amd.com /// Quiesce, suspend, and schedule activate at resume 44111627Smichael.lebeane@amd.com void quiesceTick(Tick resume) { actualTC->quiesceTick(resume); } 44211627Smichael.lebeane@amd.com 4432680Sktlim@umich.edu void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 4442190SN/A 4452680Sktlim@umich.edu void takeOverFrom(ThreadContext *oldContext) 4462680Sktlim@umich.edu { actualTC->takeOverFrom(oldContext); } 4472190SN/A 4482680Sktlim@umich.edu void regStats(const std::string &name) { actualTC->regStats(name); } 4492190SN/A 4502680Sktlim@umich.edu EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 4512235SN/A 4522680Sktlim@umich.edu Tick readLastActivate() { return actualTC->readLastActivate(); } 4532680Sktlim@umich.edu Tick readLastSuspend() { return actualTC->readLastSuspend(); } 4542254SN/A 4552680Sktlim@umich.edu void profileClear() { return actualTC->profileClear(); } 4562680Sktlim@umich.edu void profileSample() { return actualTC->profileSample(); } 4572SN/A 4582190SN/A // @todo: Do I need this? 4592680Sktlim@umich.edu void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 4602SN/A 4612680Sktlim@umich.edu void clearArchRegs() { actualTC->clearArchRegs(); } 462716SN/A 4632SN/A // 4642SN/A // New accessors for new decoder. 4652SN/A // 46613557Sgabeblack@google.com RegVal readIntReg(int reg_idx) 4672680Sktlim@umich.edu { return actualTC->readIntReg(reg_idx); } 4682SN/A 46913611Sgabeblack@google.com RegVal readFloatReg(int reg_idx) 47013611Sgabeblack@google.com { return actualTC->readFloatReg(reg_idx); } 4712SN/A 47212109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& readVecReg(const RegId& reg) const 47312109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVecReg(reg); } 47412109SRekai.GonzalezAlberquilla@arm.com 47512109SRekai.GonzalezAlberquilla@arm.com VecRegContainer& getWritableVecReg(const RegId& reg) 47612109SRekai.GonzalezAlberquilla@arm.com { return actualTC->getWritableVecReg(reg); } 47712109SRekai.GonzalezAlberquilla@arm.com 47812109SRekai.GonzalezAlberquilla@arm.com /** Vector Register Lane Interfaces. */ 47912109SRekai.GonzalezAlberquilla@arm.com /** @{ */ 48012109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 8bit operand. */ 48112109SRekai.GonzalezAlberquilla@arm.com ConstVecLane8 48212109SRekai.GonzalezAlberquilla@arm.com readVec8BitLaneReg(const RegId& reg) const 48312109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVec8BitLaneReg(reg); } 48412109SRekai.GonzalezAlberquilla@arm.com 48512109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 16bit operand. */ 48612109SRekai.GonzalezAlberquilla@arm.com ConstVecLane16 48712109SRekai.GonzalezAlberquilla@arm.com readVec16BitLaneReg(const RegId& reg) const 48812109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVec16BitLaneReg(reg); } 48912109SRekai.GonzalezAlberquilla@arm.com 49012109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 32bit operand. */ 49112109SRekai.GonzalezAlberquilla@arm.com ConstVecLane32 49212109SRekai.GonzalezAlberquilla@arm.com readVec32BitLaneReg(const RegId& reg) const 49312109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVec32BitLaneReg(reg); } 49412109SRekai.GonzalezAlberquilla@arm.com 49512109SRekai.GonzalezAlberquilla@arm.com /** Reads source vector 64bit operand. */ 49612109SRekai.GonzalezAlberquilla@arm.com ConstVecLane64 49712109SRekai.GonzalezAlberquilla@arm.com readVec64BitLaneReg(const RegId& reg) const 49812109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVec64BitLaneReg(reg); } 49912109SRekai.GonzalezAlberquilla@arm.com 50012109SRekai.GonzalezAlberquilla@arm.com /** Write a lane of the destination vector register. */ 50112109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 50212109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::Byte>& val) 50312109SRekai.GonzalezAlberquilla@arm.com { return actualTC->setVecLane(reg, val); } 50412109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 50512109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::TwoByte>& val) 50612109SRekai.GonzalezAlberquilla@arm.com { return actualTC->setVecLane(reg, val); } 50712109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 50812109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::FourByte>& val) 50912109SRekai.GonzalezAlberquilla@arm.com { return actualTC->setVecLane(reg, val); } 51012109SRekai.GonzalezAlberquilla@arm.com virtual void setVecLane(const RegId& reg, 51112109SRekai.GonzalezAlberquilla@arm.com const LaneData<LaneSize::EightByte>& val) 51212109SRekai.GonzalezAlberquilla@arm.com { return actualTC->setVecLane(reg, val); } 51312109SRekai.GonzalezAlberquilla@arm.com /** @} */ 51412109SRekai.GonzalezAlberquilla@arm.com 51512109SRekai.GonzalezAlberquilla@arm.com const VecElem& readVecElem(const RegId& reg) const 51612109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVecElem(reg); } 51712109SRekai.GonzalezAlberquilla@arm.com 51813610Sgiacomo.gabrielli@arm.com const VecPredRegContainer& readVecPredReg(const RegId& reg) const 51913610Sgiacomo.gabrielli@arm.com { return actualTC->readVecPredReg(reg); } 52013610Sgiacomo.gabrielli@arm.com 52113610Sgiacomo.gabrielli@arm.com VecPredRegContainer& getWritableVecPredReg(const RegId& reg) 52213610Sgiacomo.gabrielli@arm.com { return actualTC->getWritableVecPredReg(reg); } 52313610Sgiacomo.gabrielli@arm.com 52413622Sgabeblack@google.com RegVal readCCReg(int reg_idx) 5259920Syasuko.eckert@amd.com { return actualTC->readCCReg(reg_idx); } 5269920Syasuko.eckert@amd.com 52713557Sgabeblack@google.com void setIntReg(int reg_idx, RegVal val) 5282680Sktlim@umich.edu { actualTC->setIntReg(reg_idx, val); } 5292SN/A 53013611Sgabeblack@google.com void setFloatReg(int reg_idx, RegVal val) 53113611Sgabeblack@google.com { actualTC->setFloatReg(reg_idx, val); } 5322SN/A 53312109SRekai.GonzalezAlberquilla@arm.com void setVecReg(const RegId& reg, const VecRegContainer& val) 53412109SRekai.GonzalezAlberquilla@arm.com { actualTC->setVecReg(reg, val); } 53512109SRekai.GonzalezAlberquilla@arm.com 53613610Sgiacomo.gabrielli@arm.com void setVecPredReg(const RegId& reg, const VecPredRegContainer& val) 53713610Sgiacomo.gabrielli@arm.com { actualTC->setVecPredReg(reg, val); } 53813610Sgiacomo.gabrielli@arm.com 53912109SRekai.GonzalezAlberquilla@arm.com void setVecElem(const RegId& reg, const VecElem& val) 54012109SRekai.GonzalezAlberquilla@arm.com { actualTC->setVecElem(reg, val); } 54112109SRekai.GonzalezAlberquilla@arm.com 54213622Sgabeblack@google.com void setCCReg(int reg_idx, RegVal val) 5439920Syasuko.eckert@amd.com { actualTC->setCCReg(reg_idx, val); } 5449920Syasuko.eckert@amd.com 5457720Sgblack@eecs.umich.edu TheISA::PCState pcState() { return actualTC->pcState(); } 5462SN/A 5477720Sgblack@eecs.umich.edu void pcState(const TheISA::PCState &val) { actualTC->pcState(val); } 5482206SN/A 5498733Sgeoffrey.blake@arm.com void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); } 5508733Sgeoffrey.blake@arm.com 5517720Sgblack@eecs.umich.edu Addr instAddr() { return actualTC->instAddr(); } 5527720Sgblack@eecs.umich.edu Addr nextInstAddr() { return actualTC->nextInstAddr(); } 5537720Sgblack@eecs.umich.edu MicroPC microPC() { return actualTC->microPC(); } 5545260Sksewell@umich.edu 5557597Sminkyu.jeong@arm.com bool readPredicate() { return actualTC->readPredicate(); } 5567597Sminkyu.jeong@arm.com 5577597Sminkyu.jeong@arm.com void setPredicate(bool val) 5587597Sminkyu.jeong@arm.com { actualTC->setPredicate(val); } 5597597Sminkyu.jeong@arm.com 56013557Sgabeblack@google.com RegVal readMiscRegNoEffect(int misc_reg) const 5614172Ssaidi@eecs.umich.edu { return actualTC->readMiscRegNoEffect(misc_reg); } 5624172Ssaidi@eecs.umich.edu 56313557Sgabeblack@google.com RegVal readMiscReg(int misc_reg) 5642680Sktlim@umich.edu { return actualTC->readMiscReg(misc_reg); } 5652SN/A 56613582Sgabeblack@google.com void setMiscRegNoEffect(int misc_reg, RegVal val) 5674172Ssaidi@eecs.umich.edu { return actualTC->setMiscRegNoEffect(misc_reg, val); } 5682SN/A 56913582Sgabeblack@google.com void setMiscReg(int misc_reg, RegVal val) 5702680Sktlim@umich.edu { return actualTC->setMiscReg(misc_reg, val); } 5712SN/A 57212106SRekai.GonzalezAlberquilla@arm.com RegId flattenRegId(const RegId& regId) const 57312106SRekai.GonzalezAlberquilla@arm.com { return actualTC->flattenRegId(regId); } 57410033SAli.Saidi@ARM.com 5752190SN/A unsigned readStCondFailures() 5762680Sktlim@umich.edu { return actualTC->readStCondFailures(); } 5772190SN/A 5782190SN/A void setStCondFailures(unsigned sc_failures) 5792680Sktlim@umich.edu { actualTC->setStCondFailures(sc_failures); } 5802SN/A 58111877Sbrandon.potter@amd.com void syscall(int64_t callnum, Fault *fault) 58211877Sbrandon.potter@amd.com { actualTC->syscall(callnum, fault); } 5834111Sgblack@eecs.umich.edu 5842680Sktlim@umich.edu Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 5859426SAndreas.Sandberg@ARM.com 58613557Sgabeblack@google.com RegVal readIntRegFlat(int idx) 5879426SAndreas.Sandberg@ARM.com { return actualTC->readIntRegFlat(idx); } 5889426SAndreas.Sandberg@ARM.com 58913557Sgabeblack@google.com void setIntRegFlat(int idx, RegVal val) 5909426SAndreas.Sandberg@ARM.com { actualTC->setIntRegFlat(idx, val); } 5919426SAndreas.Sandberg@ARM.com 59213611Sgabeblack@google.com RegVal readFloatRegFlat(int idx) 59313611Sgabeblack@google.com { return actualTC->readFloatRegFlat(idx); } 5949426SAndreas.Sandberg@ARM.com 59513611Sgabeblack@google.com void setFloatRegFlat(int idx, RegVal val) 59613611Sgabeblack@google.com { actualTC->setFloatRegFlat(idx, val); } 5979920Syasuko.eckert@amd.com 59812109SRekai.GonzalezAlberquilla@arm.com const VecRegContainer& readVecRegFlat(int id) const 59912109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVecRegFlat(id); } 60012109SRekai.GonzalezAlberquilla@arm.com 60112109SRekai.GonzalezAlberquilla@arm.com VecRegContainer& getWritableVecRegFlat(int id) 60212109SRekai.GonzalezAlberquilla@arm.com { return actualTC->getWritableVecRegFlat(id); } 60312109SRekai.GonzalezAlberquilla@arm.com 60412109SRekai.GonzalezAlberquilla@arm.com void setVecRegFlat(int idx, const VecRegContainer& val) 60512109SRekai.GonzalezAlberquilla@arm.com { actualTC->setVecRegFlat(idx, val); } 60612109SRekai.GonzalezAlberquilla@arm.com 60712109SRekai.GonzalezAlberquilla@arm.com const VecElem& readVecElemFlat(const RegIndex& id, 60812109SRekai.GonzalezAlberquilla@arm.com const ElemIndex& elemIndex) const 60912109SRekai.GonzalezAlberquilla@arm.com { return actualTC->readVecElemFlat(id, elemIndex); } 61012109SRekai.GonzalezAlberquilla@arm.com 61112109SRekai.GonzalezAlberquilla@arm.com void setVecElemFlat(const RegIndex& id, const ElemIndex& elemIndex, 61212109SRekai.GonzalezAlberquilla@arm.com const VecElem& val) 61312109SRekai.GonzalezAlberquilla@arm.com { actualTC->setVecElemFlat(id, elemIndex, val); } 61412109SRekai.GonzalezAlberquilla@arm.com 61513610Sgiacomo.gabrielli@arm.com const VecPredRegContainer& readVecPredRegFlat(int id) const 61613610Sgiacomo.gabrielli@arm.com { return actualTC->readVecPredRegFlat(id); } 61713610Sgiacomo.gabrielli@arm.com 61813610Sgiacomo.gabrielli@arm.com VecPredRegContainer& getWritableVecPredRegFlat(int id) 61913610Sgiacomo.gabrielli@arm.com { return actualTC->getWritableVecPredRegFlat(id); } 62013610Sgiacomo.gabrielli@arm.com 62113610Sgiacomo.gabrielli@arm.com void setVecPredRegFlat(int idx, const VecPredRegContainer& val) 62213610Sgiacomo.gabrielli@arm.com { actualTC->setVecPredRegFlat(idx, val); } 62313610Sgiacomo.gabrielli@arm.com 62413622Sgabeblack@google.com RegVal readCCRegFlat(int idx) 6259920Syasuko.eckert@amd.com { return actualTC->readCCRegFlat(idx); } 6269920Syasuko.eckert@amd.com 62713622Sgabeblack@google.com void setCCRegFlat(int idx, RegVal val) 6289920Syasuko.eckert@amd.com { actualTC->setCCRegFlat(idx, val); } 6292SN/A}; 6302SN/A 6319428SAndreas.Sandberg@ARM.com/** @{ */ 6329428SAndreas.Sandberg@ARM.com/** 6339428SAndreas.Sandberg@ARM.com * Thread context serialization helpers 6349428SAndreas.Sandberg@ARM.com * 6359428SAndreas.Sandberg@ARM.com * These helper functions provide a way to the data in a 6369428SAndreas.Sandberg@ARM.com * ThreadContext. They are provided as separate helper function since 6379428SAndreas.Sandberg@ARM.com * implementing them as members of the ThreadContext interface would 6389428SAndreas.Sandberg@ARM.com * be confusing when the ThreadContext is exported via a proxy. 6399428SAndreas.Sandberg@ARM.com */ 6409428SAndreas.Sandberg@ARM.com 64110905Sandreas.sandberg@arm.comvoid serialize(ThreadContext &tc, CheckpointOut &cp); 64210905Sandreas.sandberg@arm.comvoid unserialize(ThreadContext &tc, CheckpointIn &cp); 6439428SAndreas.Sandberg@ARM.com 6449428SAndreas.Sandberg@ARM.com/** @} */ 6459428SAndreas.Sandberg@ARM.com 6469441SAndreas.Sandberg@ARM.com 6479441SAndreas.Sandberg@ARM.com/** 6489441SAndreas.Sandberg@ARM.com * Copy state between thread contexts in preparation for CPU handover. 6499441SAndreas.Sandberg@ARM.com * 6509441SAndreas.Sandberg@ARM.com * @note This method modifies the old thread contexts as well as the 6519441SAndreas.Sandberg@ARM.com * new thread context. The old thread context will have its quiesce 6529441SAndreas.Sandberg@ARM.com * event descheduled if it is scheduled and its status set to halted. 6539441SAndreas.Sandberg@ARM.com * 6549441SAndreas.Sandberg@ARM.com * @param new_tc Destination ThreadContext. 6559441SAndreas.Sandberg@ARM.com * @param old_tc Source ThreadContext. 6569441SAndreas.Sandberg@ARM.com */ 6579441SAndreas.Sandberg@ARM.comvoid takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc); 6589441SAndreas.Sandberg@ARM.com 6592190SN/A#endif 660