thread_context.hh revision 12106
12SN/A/* 29428SAndreas.Sandberg@ARM.com * Copyright (c) 2011-2012 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152190SN/A * Copyright (c) 2006 The Regents of The University of Michigan 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665SN/A * 412665SN/A * Authors: Kevin Lim 422SN/A */ 432SN/A 442680Sktlim@umich.edu#ifndef __CPU_THREAD_CONTEXT_HH__ 452680Sktlim@umich.edu#define __CPU_THREAD_CONTEXT_HH__ 462SN/A 478229Snate@binkert.org#include <iostream> 487680Sgblack@eecs.umich.edu#include <string> 497680Sgblack@eecs.umich.edu 506329Sgblack@eecs.umich.edu#include "arch/registers.hh" 513453Sgblack@eecs.umich.edu#include "arch/types.hh" 526216Snate@binkert.org#include "base/types.hh" 536658Snate@binkert.org#include "config/the_isa.hh" 5412104Snathanael.premillieu@arm.com#include "cpu/reg_class.hh" 552SN/A 562190SN/A// @todo: Figure out a more architecture independent way to obtain the ITB and 572190SN/A// DTB pointers. 583453Sgblack@eecs.umich.edunamespace TheISA 593453Sgblack@eecs.umich.edu{ 609020Sgblack@eecs.umich.edu class Decoder; 616022Sgblack@eecs.umich.edu class TLB; 623453Sgblack@eecs.umich.edu} 632190SN/Aclass BaseCPU; 648887Sgeoffrey.blake@arm.comclass CheckerCPU; 657680Sgblack@eecs.umich.educlass Checkpoint; 662313SN/Aclass EndQuiesceEvent; 678706Sandreas.hansson@arm.comclass SETranslatingPortProxy; 688706Sandreas.hansson@arm.comclass FSTranslatingPortProxy; 698706Sandreas.hansson@arm.comclass PortProxy; 702190SN/Aclass Process; 712190SN/Aclass System; 723548Sgblack@eecs.umich.edunamespace TheISA { 733548Sgblack@eecs.umich.edu namespace Kernel { 743548Sgblack@eecs.umich.edu class Statistics; 758902Sandreas.hansson@arm.com } 768902Sandreas.hansson@arm.com} 772SN/A 782680Sktlim@umich.edu/** 792680Sktlim@umich.edu * ThreadContext is the external interface to all thread state for 802680Sktlim@umich.edu * anything outside of the CPU. It provides all accessor methods to 812680Sktlim@umich.edu * state that might be needed by external objects, ranging from 822680Sktlim@umich.edu * register values to things such as kernel stats. It is an abstract 832680Sktlim@umich.edu * base class; the CPU can create its own ThreadContext by either 842680Sktlim@umich.edu * deriving from it, or using the templated ProxyThreadContext. 852680Sktlim@umich.edu * 862680Sktlim@umich.edu * The ThreadContext is slightly different than the ExecContext. The 872680Sktlim@umich.edu * ThreadContext provides access to an individual thread's state; an 882680Sktlim@umich.edu * ExecContext provides ISA access to the CPU (meaning it is 892682Sktlim@umich.edu * implicitly multithreaded on SMT systems). Additionally the 902680Sktlim@umich.edu * ThreadState is an abstract class that exactly defines the 912680Sktlim@umich.edu * interface; the ExecContext is a more implicit interface that must 922680Sktlim@umich.edu * be implemented so that the ISA can access whatever state it needs. 932680Sktlim@umich.edu */ 942680Sktlim@umich.educlass ThreadContext 952SN/A{ 962107SN/A protected: 972107SN/A typedef TheISA::MachInst MachInst; 982190SN/A typedef TheISA::IntReg IntReg; 992455SN/A typedef TheISA::FloatReg FloatReg; 1002455SN/A typedef TheISA::FloatRegBits FloatRegBits; 1019920Syasuko.eckert@amd.com typedef TheISA::CCReg CCReg; 1022159SN/A typedef TheISA::MiscReg MiscReg; 1032SN/A public: 1046029Ssteve.reinhardt@amd.com 105246SN/A enum Status 106246SN/A { 107246SN/A /// Running. Instructions should be executed only when 108246SN/A /// the context is in this state. 109246SN/A Active, 110246SN/A 111246SN/A /// Temporarily inactive. Entered while waiting for 1122190SN/A /// synchronization, etc. 113246SN/A Suspended, 114246SN/A 115246SN/A /// Permanently shut down. Entered when target executes 116246SN/A /// m5exit pseudo-instruction. When all contexts enter 117246SN/A /// this state, the simulation will terminate. 118246SN/A Halted 119246SN/A }; 1202SN/A 1212680Sktlim@umich.edu virtual ~ThreadContext() { }; 1222423SN/A 1232190SN/A virtual BaseCPU *getCpuPtr() = 0; 124180SN/A 12510110Sandreas.hansson@arm.com virtual int cpuId() const = 0; 1262190SN/A 12710190Sakash.bagdia@arm.com virtual uint32_t socketId() const = 0; 12810190Sakash.bagdia@arm.com 12910110Sandreas.hansson@arm.com virtual int threadId() const = 0; 1305715Shsul@eecs.umich.edu 1315715Shsul@eecs.umich.edu virtual void setThreadId(int id) = 0; 1325714Shsul@eecs.umich.edu 13310110Sandreas.hansson@arm.com virtual int contextId() const = 0; 1345714Shsul@eecs.umich.edu 1355714Shsul@eecs.umich.edu virtual void setContextId(int id) = 0; 1365714Shsul@eecs.umich.edu 1376022Sgblack@eecs.umich.edu virtual TheISA::TLB *getITBPtr() = 0; 1382190SN/A 1396022Sgblack@eecs.umich.edu virtual TheISA::TLB *getDTBPtr() = 0; 1402521SN/A 1418887Sgeoffrey.blake@arm.com virtual CheckerCPU *getCheckerCpuPtr() = 0; 1428733Sgeoffrey.blake@arm.com 1439020Sgblack@eecs.umich.edu virtual TheISA::Decoder *getDecoderPtr() = 0; 1448541Sgblack@eecs.umich.edu 1454997Sgblack@eecs.umich.edu virtual System *getSystemPtr() = 0; 1464997Sgblack@eecs.umich.edu 1473548Sgblack@eecs.umich.edu virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 1482654SN/A 1498852Sandreas.hansson@arm.com virtual PortProxy &getPhysProxy() = 0; 1502521SN/A 1518852Sandreas.hansson@arm.com virtual FSTranslatingPortProxy &getVirtProxy() = 0; 1523673Srdreslin@umich.edu 1538706Sandreas.hansson@arm.com /** 1548706Sandreas.hansson@arm.com * Initialise the physical and virtual port proxies and tie them to 1558706Sandreas.hansson@arm.com * the data port of the CPU. 1568706Sandreas.hansson@arm.com * 1578706Sandreas.hansson@arm.com * tc ThreadContext for the virtual-to-physical translation 1588706Sandreas.hansson@arm.com */ 1598706Sandreas.hansson@arm.com virtual void initMemProxies(ThreadContext *tc) = 0; 1608799Sgblack@eecs.umich.edu 1618852Sandreas.hansson@arm.com virtual SETranslatingPortProxy &getMemProxy() = 0; 1622518SN/A 1632190SN/A virtual Process *getProcessPtr() = 0; 1642190SN/A 16511886Sbrandon.potter@amd.com virtual void setProcessPtr(Process *p) = 0; 16611886Sbrandon.potter@amd.com 1672190SN/A virtual Status status() const = 0; 1682159SN/A 1692235SN/A virtual void setStatus(Status new_status) = 0; 1702103SN/A 17110407Smitch.hayenga@arm.com /// Set the status to Active. 17210407Smitch.hayenga@arm.com virtual void activate() = 0; 173393SN/A 174393SN/A /// Set the status to Suspended. 17510407Smitch.hayenga@arm.com virtual void suspend() = 0; 176393SN/A 177393SN/A /// Set the status to Halted. 17810407Smitch.hayenga@arm.com virtual void halt() = 0; 1792159SN/A 18011627Smichael.lebeane@amd.com /// Quiesce thread context 18111627Smichael.lebeane@amd.com void quiesce(); 18211627Smichael.lebeane@amd.com 18311627Smichael.lebeane@amd.com /// Quiesce, suspend, and schedule activate at resume 18411627Smichael.lebeane@amd.com void quiesceTick(Tick resume); 18511627Smichael.lebeane@amd.com 1862190SN/A virtual void dumpFuncProfile() = 0; 1872159SN/A 1882680Sktlim@umich.edu virtual void takeOverFrom(ThreadContext *old_context) = 0; 1892159SN/A 1902190SN/A virtual void regStats(const std::string &name) = 0; 1912159SN/A 1922313SN/A virtual EndQuiesceEvent *getQuiesceEvent() = 0; 1932235SN/A 1942235SN/A // Not necessarily the best location for these... 1952235SN/A // Having an extra function just to read these is obnoxious 1962235SN/A virtual Tick readLastActivate() = 0; 1972235SN/A virtual Tick readLastSuspend() = 0; 1982254SN/A 1992254SN/A virtual void profileClear() = 0; 2002254SN/A virtual void profileSample() = 0; 2012235SN/A 2022680Sktlim@umich.edu virtual void copyArchRegs(ThreadContext *tc) = 0; 2032159SN/A 2042190SN/A virtual void clearArchRegs() = 0; 2052159SN/A 2062159SN/A // 2072159SN/A // New accessors for new decoder. 2082159SN/A // 2092190SN/A virtual uint64_t readIntReg(int reg_idx) = 0; 2102159SN/A 2112455SN/A virtual FloatReg readFloatReg(int reg_idx) = 0; 2122159SN/A 2132455SN/A virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 2142159SN/A 2159920Syasuko.eckert@amd.com virtual CCReg readCCReg(int reg_idx) = 0; 2169920Syasuko.eckert@amd.com 2172190SN/A virtual void setIntReg(int reg_idx, uint64_t val) = 0; 2182159SN/A 2192455SN/A virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 2202159SN/A 2212455SN/A virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 2222455SN/A 2239920Syasuko.eckert@amd.com virtual void setCCReg(int reg_idx, CCReg val) = 0; 2249920Syasuko.eckert@amd.com 2257720Sgblack@eecs.umich.edu virtual TheISA::PCState pcState() = 0; 2262159SN/A 2277720Sgblack@eecs.umich.edu virtual void pcState(const TheISA::PCState &val) = 0; 2282159SN/A 22911886Sbrandon.potter@amd.com void 23011886Sbrandon.potter@amd.com setNPC(Addr val) 23111886Sbrandon.potter@amd.com { 23211886Sbrandon.potter@amd.com TheISA::PCState pc_state = pcState(); 23311886Sbrandon.potter@amd.com pc_state.setNPC(val); 23411886Sbrandon.potter@amd.com pcState(pc_state); 23511886Sbrandon.potter@amd.com } 23611886Sbrandon.potter@amd.com 2378733Sgeoffrey.blake@arm.com virtual void pcStateNoRecord(const TheISA::PCState &val) = 0; 2388733Sgeoffrey.blake@arm.com 2397720Sgblack@eecs.umich.edu virtual Addr instAddr() = 0; 2402159SN/A 2417720Sgblack@eecs.umich.edu virtual Addr nextInstAddr() = 0; 2422159SN/A 2437720Sgblack@eecs.umich.edu virtual MicroPC microPC() = 0; 2445260Sksewell@umich.edu 24510698Sandreas.hansson@arm.com virtual MiscReg readMiscRegNoEffect(int misc_reg) const = 0; 2464172Ssaidi@eecs.umich.edu 2472190SN/A virtual MiscReg readMiscReg(int misc_reg) = 0; 2482159SN/A 2494172Ssaidi@eecs.umich.edu virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; 2502190SN/A 2513468Sgblack@eecs.umich.edu virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 2522190SN/A 25312106SRekai.GonzalezAlberquilla@arm.com virtual RegId flattenRegId(const RegId& regId) const = 0; 2546313Sgblack@eecs.umich.edu 2556221Snate@binkert.org virtual uint64_t 25612106SRekai.GonzalezAlberquilla@arm.com readRegOtherThread(const RegId& misc_reg, ThreadID tid) 2576221Snate@binkert.org { 2586221Snate@binkert.org return 0; 2596221Snate@binkert.org } 2604661Sksewell@umich.edu 2616221Snate@binkert.org virtual void 26212106SRekai.GonzalezAlberquilla@arm.com setRegOtherThread(const RegId& misc_reg, const MiscReg &val, ThreadID tid) 2636221Snate@binkert.org { 2646221Snate@binkert.org } 2654661Sksewell@umich.edu 2662235SN/A // Also not necessarily the best location for these two. Hopefully will go 2672235SN/A // away once we decide upon where st cond failures goes. 2682190SN/A virtual unsigned readStCondFailures() = 0; 2692190SN/A 2702190SN/A virtual void setStCondFailures(unsigned sc_failures) = 0; 2712159SN/A 2722235SN/A // Same with st cond failures. 2732190SN/A virtual Counter readFuncExeInst() = 0; 2742834Sksewell@umich.edu 27511877Sbrandon.potter@amd.com virtual void syscall(int64_t callnum, Fault *fault) = 0; 2764111Sgblack@eecs.umich.edu 2772834Sksewell@umich.edu // This function exits the thread context in the CPU and returns 2782834Sksewell@umich.edu // 1 if the CPU has no more active threads (meaning it's OK to exit); 2792834Sksewell@umich.edu // Used in syscall-emulation mode when a thread calls the exit syscall. 2802834Sksewell@umich.edu virtual int exit() { return 1; }; 2812525SN/A 2825217Ssaidi@eecs.umich.edu /** function to compare two thread contexts (for debugging) */ 2835217Ssaidi@eecs.umich.edu static void compare(ThreadContext *one, ThreadContext *two); 2849426SAndreas.Sandberg@ARM.com 2859426SAndreas.Sandberg@ARM.com /** @{ */ 2869426SAndreas.Sandberg@ARM.com /** 2879426SAndreas.Sandberg@ARM.com * Flat register interfaces 2889426SAndreas.Sandberg@ARM.com * 2899426SAndreas.Sandberg@ARM.com * Some architectures have different registers visible in 2909426SAndreas.Sandberg@ARM.com * different modes. Such architectures "flatten" a register (see 29112106SRekai.GonzalezAlberquilla@arm.com * flattenRegId()) to map it into the 2929426SAndreas.Sandberg@ARM.com * gem5 register file. This interface provides a flat interface to 2939426SAndreas.Sandberg@ARM.com * the underlying register file, which allows for example 2949426SAndreas.Sandberg@ARM.com * serialization code to access all registers. 2959426SAndreas.Sandberg@ARM.com */ 2969426SAndreas.Sandberg@ARM.com 2979426SAndreas.Sandberg@ARM.com virtual uint64_t readIntRegFlat(int idx) = 0; 2989426SAndreas.Sandberg@ARM.com virtual void setIntRegFlat(int idx, uint64_t val) = 0; 2999426SAndreas.Sandberg@ARM.com 3009426SAndreas.Sandberg@ARM.com virtual FloatReg readFloatRegFlat(int idx) = 0; 3019426SAndreas.Sandberg@ARM.com virtual void setFloatRegFlat(int idx, FloatReg val) = 0; 3029426SAndreas.Sandberg@ARM.com 3039426SAndreas.Sandberg@ARM.com virtual FloatRegBits readFloatRegBitsFlat(int idx) = 0; 3049426SAndreas.Sandberg@ARM.com virtual void setFloatRegBitsFlat(int idx, FloatRegBits val) = 0; 3059426SAndreas.Sandberg@ARM.com 3069920Syasuko.eckert@amd.com virtual CCReg readCCRegFlat(int idx) = 0; 3079920Syasuko.eckert@amd.com virtual void setCCRegFlat(int idx, CCReg val) = 0; 3089426SAndreas.Sandberg@ARM.com /** @} */ 3099426SAndreas.Sandberg@ARM.com 3102159SN/A}; 3112159SN/A 3122682Sktlim@umich.edu/** 3132682Sktlim@umich.edu * ProxyThreadContext class that provides a way to implement a 3142682Sktlim@umich.edu * ThreadContext without having to derive from it. ThreadContext is an 3152682Sktlim@umich.edu * abstract class, so anything that derives from it and uses its 3162682Sktlim@umich.edu * interface will pay the overhead of virtual function calls. This 3172682Sktlim@umich.edu * class is created to enable a user-defined Thread object to be used 3182682Sktlim@umich.edu * wherever ThreadContexts are used, without paying the overhead of 3192682Sktlim@umich.edu * virtual function calls when it is used by itself. See 3202682Sktlim@umich.edu * simple_thread.hh for an example of this. 3212682Sktlim@umich.edu */ 3222680Sktlim@umich.edutemplate <class TC> 3232680Sktlim@umich.educlass ProxyThreadContext : public ThreadContext 3242190SN/A{ 3252190SN/A public: 3262680Sktlim@umich.edu ProxyThreadContext(TC *actual_tc) 3272680Sktlim@umich.edu { actualTC = actual_tc; } 3282159SN/A 3292190SN/A private: 3302680Sktlim@umich.edu TC *actualTC; 3312SN/A 3322SN/A public: 3332SN/A 3342680Sktlim@umich.edu BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 3352SN/A 33610110Sandreas.hansson@arm.com int cpuId() const { return actualTC->cpuId(); } 3372SN/A 33810190Sakash.bagdia@arm.com uint32_t socketId() const { return actualTC->socketId(); } 33910190Sakash.bagdia@arm.com 34010110Sandreas.hansson@arm.com int threadId() const { return actualTC->threadId(); } 3415715Shsul@eecs.umich.edu 34210110Sandreas.hansson@arm.com void setThreadId(int id) { actualTC->setThreadId(id); } 3435714Shsul@eecs.umich.edu 34410110Sandreas.hansson@arm.com int contextId() const { return actualTC->contextId(); } 3455714Shsul@eecs.umich.edu 3465714Shsul@eecs.umich.edu void setContextId(int id) { actualTC->setContextId(id); } 3475714Shsul@eecs.umich.edu 3486022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 3491917SN/A 3506022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 3512521SN/A 3528887Sgeoffrey.blake@arm.com CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); } 3538733Sgeoffrey.blake@arm.com 3549020Sgblack@eecs.umich.edu TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); } 3558541Sgblack@eecs.umich.edu 3564997Sgblack@eecs.umich.edu System *getSystemPtr() { return actualTC->getSystemPtr(); } 3574997Sgblack@eecs.umich.edu 3583548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *getKernelStats() 3593548Sgblack@eecs.umich.edu { return actualTC->getKernelStats(); } 3602654SN/A 3618852Sandreas.hansson@arm.com PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); } 3622521SN/A 3638852Sandreas.hansson@arm.com FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); } 3643673Srdreslin@umich.edu 3658706Sandreas.hansson@arm.com void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); } 3668799Sgblack@eecs.umich.edu 3678852Sandreas.hansson@arm.com SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); } 3682518SN/A 3692680Sktlim@umich.edu Process *getProcessPtr() { return actualTC->getProcessPtr(); } 3702SN/A 37111886Sbrandon.potter@amd.com void setProcessPtr(Process *p) { actualTC->setProcessPtr(p); } 37211886Sbrandon.potter@amd.com 3732680Sktlim@umich.edu Status status() const { return actualTC->status(); } 374595SN/A 3752680Sktlim@umich.edu void setStatus(Status new_status) { actualTC->setStatus(new_status); } 3762SN/A 37710407Smitch.hayenga@arm.com /// Set the status to Active. 37810407Smitch.hayenga@arm.com void activate() { actualTC->activate(); } 3792SN/A 3802190SN/A /// Set the status to Suspended. 38110407Smitch.hayenga@arm.com void suspend() { actualTC->suspend(); } 3822SN/A 3832190SN/A /// Set the status to Halted. 38410407Smitch.hayenga@arm.com void halt() { actualTC->halt(); } 385217SN/A 38611627Smichael.lebeane@amd.com /// Quiesce thread context 38711627Smichael.lebeane@amd.com void quiesce() { actualTC->quiesce(); } 38811627Smichael.lebeane@amd.com 38911627Smichael.lebeane@amd.com /// Quiesce, suspend, and schedule activate at resume 39011627Smichael.lebeane@amd.com void quiesceTick(Tick resume) { actualTC->quiesceTick(resume); } 39111627Smichael.lebeane@amd.com 3922680Sktlim@umich.edu void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 3932190SN/A 3942680Sktlim@umich.edu void takeOverFrom(ThreadContext *oldContext) 3952680Sktlim@umich.edu { actualTC->takeOverFrom(oldContext); } 3962190SN/A 3972680Sktlim@umich.edu void regStats(const std::string &name) { actualTC->regStats(name); } 3982190SN/A 3992680Sktlim@umich.edu EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 4002235SN/A 4012680Sktlim@umich.edu Tick readLastActivate() { return actualTC->readLastActivate(); } 4022680Sktlim@umich.edu Tick readLastSuspend() { return actualTC->readLastSuspend(); } 4032254SN/A 4042680Sktlim@umich.edu void profileClear() { return actualTC->profileClear(); } 4052680Sktlim@umich.edu void profileSample() { return actualTC->profileSample(); } 4062SN/A 4072190SN/A // @todo: Do I need this? 4082680Sktlim@umich.edu void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 4092SN/A 4102680Sktlim@umich.edu void clearArchRegs() { actualTC->clearArchRegs(); } 411716SN/A 4122SN/A // 4132SN/A // New accessors for new decoder. 4142SN/A // 4152SN/A uint64_t readIntReg(int reg_idx) 4162680Sktlim@umich.edu { return actualTC->readIntReg(reg_idx); } 4172SN/A 4182455SN/A FloatReg readFloatReg(int reg_idx) 4192680Sktlim@umich.edu { return actualTC->readFloatReg(reg_idx); } 4202SN/A 4212455SN/A FloatRegBits readFloatRegBits(int reg_idx) 4222680Sktlim@umich.edu { return actualTC->readFloatRegBits(reg_idx); } 4232SN/A 4249920Syasuko.eckert@amd.com CCReg readCCReg(int reg_idx) 4259920Syasuko.eckert@amd.com { return actualTC->readCCReg(reg_idx); } 4269920Syasuko.eckert@amd.com 4272SN/A void setIntReg(int reg_idx, uint64_t val) 4282680Sktlim@umich.edu { actualTC->setIntReg(reg_idx, val); } 4292SN/A 4302455SN/A void setFloatReg(int reg_idx, FloatReg val) 4312680Sktlim@umich.edu { actualTC->setFloatReg(reg_idx, val); } 4322SN/A 4332455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 4342680Sktlim@umich.edu { actualTC->setFloatRegBits(reg_idx, val); } 4352SN/A 4369920Syasuko.eckert@amd.com void setCCReg(int reg_idx, CCReg val) 4379920Syasuko.eckert@amd.com { actualTC->setCCReg(reg_idx, val); } 4389920Syasuko.eckert@amd.com 4397720Sgblack@eecs.umich.edu TheISA::PCState pcState() { return actualTC->pcState(); } 4402SN/A 4417720Sgblack@eecs.umich.edu void pcState(const TheISA::PCState &val) { actualTC->pcState(val); } 4422206SN/A 4438733Sgeoffrey.blake@arm.com void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); } 4448733Sgeoffrey.blake@arm.com 4457720Sgblack@eecs.umich.edu Addr instAddr() { return actualTC->instAddr(); } 4467720Sgblack@eecs.umich.edu Addr nextInstAddr() { return actualTC->nextInstAddr(); } 4477720Sgblack@eecs.umich.edu MicroPC microPC() { return actualTC->microPC(); } 4485260Sksewell@umich.edu 4497597Sminkyu.jeong@arm.com bool readPredicate() { return actualTC->readPredicate(); } 4507597Sminkyu.jeong@arm.com 4517597Sminkyu.jeong@arm.com void setPredicate(bool val) 4527597Sminkyu.jeong@arm.com { actualTC->setPredicate(val); } 4537597Sminkyu.jeong@arm.com 45410698Sandreas.hansson@arm.com MiscReg readMiscRegNoEffect(int misc_reg) const 4554172Ssaidi@eecs.umich.edu { return actualTC->readMiscRegNoEffect(misc_reg); } 4564172Ssaidi@eecs.umich.edu 4572159SN/A MiscReg readMiscReg(int misc_reg) 4582680Sktlim@umich.edu { return actualTC->readMiscReg(misc_reg); } 4592SN/A 4604172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 4614172Ssaidi@eecs.umich.edu { return actualTC->setMiscRegNoEffect(misc_reg, val); } 4622SN/A 4633468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 4642680Sktlim@umich.edu { return actualTC->setMiscReg(misc_reg, val); } 4652SN/A 46612106SRekai.GonzalezAlberquilla@arm.com RegId flattenRegId(const RegId& regId) const 46712106SRekai.GonzalezAlberquilla@arm.com { return actualTC->flattenRegId(regId); } 46810033SAli.Saidi@ARM.com 4692190SN/A unsigned readStCondFailures() 4702680Sktlim@umich.edu { return actualTC->readStCondFailures(); } 4712190SN/A 4722190SN/A void setStCondFailures(unsigned sc_failures) 4732680Sktlim@umich.edu { actualTC->setStCondFailures(sc_failures); } 4742SN/A 47511877Sbrandon.potter@amd.com void syscall(int64_t callnum, Fault *fault) 47611877Sbrandon.potter@amd.com { actualTC->syscall(callnum, fault); } 4774111Sgblack@eecs.umich.edu 4782680Sktlim@umich.edu Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 4799426SAndreas.Sandberg@ARM.com 4809426SAndreas.Sandberg@ARM.com uint64_t readIntRegFlat(int idx) 4819426SAndreas.Sandberg@ARM.com { return actualTC->readIntRegFlat(idx); } 4829426SAndreas.Sandberg@ARM.com 4839426SAndreas.Sandberg@ARM.com void setIntRegFlat(int idx, uint64_t val) 4849426SAndreas.Sandberg@ARM.com { actualTC->setIntRegFlat(idx, val); } 4859426SAndreas.Sandberg@ARM.com 4869426SAndreas.Sandberg@ARM.com FloatReg readFloatRegFlat(int idx) 4879426SAndreas.Sandberg@ARM.com { return actualTC->readFloatRegFlat(idx); } 4889426SAndreas.Sandberg@ARM.com 4899426SAndreas.Sandberg@ARM.com void setFloatRegFlat(int idx, FloatReg val) 4909426SAndreas.Sandberg@ARM.com { actualTC->setFloatRegFlat(idx, val); } 4919426SAndreas.Sandberg@ARM.com 4929426SAndreas.Sandberg@ARM.com FloatRegBits readFloatRegBitsFlat(int idx) 4939426SAndreas.Sandberg@ARM.com { return actualTC->readFloatRegBitsFlat(idx); } 4949426SAndreas.Sandberg@ARM.com 4959426SAndreas.Sandberg@ARM.com void setFloatRegBitsFlat(int idx, FloatRegBits val) 4969426SAndreas.Sandberg@ARM.com { actualTC->setFloatRegBitsFlat(idx, val); } 4979920Syasuko.eckert@amd.com 4989920Syasuko.eckert@amd.com CCReg readCCRegFlat(int idx) 4999920Syasuko.eckert@amd.com { return actualTC->readCCRegFlat(idx); } 5009920Syasuko.eckert@amd.com 5019920Syasuko.eckert@amd.com void setCCRegFlat(int idx, CCReg val) 5029920Syasuko.eckert@amd.com { actualTC->setCCRegFlat(idx, val); } 5032SN/A}; 5042SN/A 5059428SAndreas.Sandberg@ARM.com/** @{ */ 5069428SAndreas.Sandberg@ARM.com/** 5079428SAndreas.Sandberg@ARM.com * Thread context serialization helpers 5089428SAndreas.Sandberg@ARM.com * 5099428SAndreas.Sandberg@ARM.com * These helper functions provide a way to the data in a 5109428SAndreas.Sandberg@ARM.com * ThreadContext. They are provided as separate helper function since 5119428SAndreas.Sandberg@ARM.com * implementing them as members of the ThreadContext interface would 5129428SAndreas.Sandberg@ARM.com * be confusing when the ThreadContext is exported via a proxy. 5139428SAndreas.Sandberg@ARM.com */ 5149428SAndreas.Sandberg@ARM.com 51510905Sandreas.sandberg@arm.comvoid serialize(ThreadContext &tc, CheckpointOut &cp); 51610905Sandreas.sandberg@arm.comvoid unserialize(ThreadContext &tc, CheckpointIn &cp); 5179428SAndreas.Sandberg@ARM.com 5189428SAndreas.Sandberg@ARM.com/** @} */ 5199428SAndreas.Sandberg@ARM.com 5209441SAndreas.Sandberg@ARM.com 5219441SAndreas.Sandberg@ARM.com/** 5229441SAndreas.Sandberg@ARM.com * Copy state between thread contexts in preparation for CPU handover. 5239441SAndreas.Sandberg@ARM.com * 5249441SAndreas.Sandberg@ARM.com * @note This method modifies the old thread contexts as well as the 5259441SAndreas.Sandberg@ARM.com * new thread context. The old thread context will have its quiesce 5269441SAndreas.Sandberg@ARM.com * event descheduled if it is scheduled and its status set to halted. 5279441SAndreas.Sandberg@ARM.com * 5289441SAndreas.Sandberg@ARM.com * @param new_tc Destination ThreadContext. 5299441SAndreas.Sandberg@ARM.com * @param old_tc Source ThreadContext. 5309441SAndreas.Sandberg@ARM.com */ 5319441SAndreas.Sandberg@ARM.comvoid takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc); 5329441SAndreas.Sandberg@ARM.com 5332190SN/A#endif 534