thread_context.hh revision 10190
12SN/A/* 29428SAndreas.Sandberg@ARM.com * Copyright (c) 2011-2012 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 48733Sgeoffrey.blake@arm.com * All rights reserved 58733Sgeoffrey.blake@arm.com * 68733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 78733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 88733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 98733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 108733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 118733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 128733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 138733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 148733Sgeoffrey.blake@arm.com * 152190SN/A * Copyright (c) 2006 The Regents of The University of Michigan 162SN/A * All rights reserved. 172SN/A * 182SN/A * Redistribution and use in source and binary forms, with or without 192SN/A * modification, are permitted provided that the following conditions are 202SN/A * met: redistributions of source code must retain the above copyright 212SN/A * notice, this list of conditions and the following disclaimer; 222SN/A * redistributions in binary form must reproduce the above copyright 232SN/A * notice, this list of conditions and the following disclaimer in the 242SN/A * documentation and/or other materials provided with the distribution; 252SN/A * neither the name of the copyright holders nor the names of its 262SN/A * contributors may be used to endorse or promote products derived from 272SN/A * this software without specific prior written permission. 282SN/A * 292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665SN/A * 412665SN/A * Authors: Kevin Lim 422SN/A */ 432SN/A 442680Sktlim@umich.edu#ifndef __CPU_THREAD_CONTEXT_HH__ 452680Sktlim@umich.edu#define __CPU_THREAD_CONTEXT_HH__ 462SN/A 478229Snate@binkert.org#include <iostream> 487680Sgblack@eecs.umich.edu#include <string> 497680Sgblack@eecs.umich.edu 506329Sgblack@eecs.umich.edu#include "arch/registers.hh" 513453Sgblack@eecs.umich.edu#include "arch/types.hh" 526216Snate@binkert.org#include "base/types.hh" 536658Snate@binkert.org#include "config/the_isa.hh" 542SN/A 552190SN/A// @todo: Figure out a more architecture independent way to obtain the ITB and 562190SN/A// DTB pointers. 573453Sgblack@eecs.umich.edunamespace TheISA 583453Sgblack@eecs.umich.edu{ 599020Sgblack@eecs.umich.edu class Decoder; 606022Sgblack@eecs.umich.edu class TLB; 613453Sgblack@eecs.umich.edu} 622190SN/Aclass BaseCPU; 638887Sgeoffrey.blake@arm.comclass CheckerCPU; 647680Sgblack@eecs.umich.educlass Checkpoint; 652313SN/Aclass EndQuiesceEvent; 668706Sandreas.hansson@arm.comclass SETranslatingPortProxy; 678706Sandreas.hansson@arm.comclass FSTranslatingPortProxy; 688706Sandreas.hansson@arm.comclass PortProxy; 692190SN/Aclass Process; 702190SN/Aclass System; 713548Sgblack@eecs.umich.edunamespace TheISA { 723548Sgblack@eecs.umich.edu namespace Kernel { 733548Sgblack@eecs.umich.edu class Statistics; 748902Sandreas.hansson@arm.com } 758902Sandreas.hansson@arm.com} 762SN/A 772680Sktlim@umich.edu/** 782680Sktlim@umich.edu * ThreadContext is the external interface to all thread state for 792680Sktlim@umich.edu * anything outside of the CPU. It provides all accessor methods to 802680Sktlim@umich.edu * state that might be needed by external objects, ranging from 812680Sktlim@umich.edu * register values to things such as kernel stats. It is an abstract 822680Sktlim@umich.edu * base class; the CPU can create its own ThreadContext by either 832680Sktlim@umich.edu * deriving from it, or using the templated ProxyThreadContext. 842680Sktlim@umich.edu * 852680Sktlim@umich.edu * The ThreadContext is slightly different than the ExecContext. The 862680Sktlim@umich.edu * ThreadContext provides access to an individual thread's state; an 872680Sktlim@umich.edu * ExecContext provides ISA access to the CPU (meaning it is 882682Sktlim@umich.edu * implicitly multithreaded on SMT systems). Additionally the 892680Sktlim@umich.edu * ThreadState is an abstract class that exactly defines the 902680Sktlim@umich.edu * interface; the ExecContext is a more implicit interface that must 912680Sktlim@umich.edu * be implemented so that the ISA can access whatever state it needs. 922680Sktlim@umich.edu */ 932680Sktlim@umich.educlass ThreadContext 942SN/A{ 952107SN/A protected: 962107SN/A typedef TheISA::MachInst MachInst; 972190SN/A typedef TheISA::IntReg IntReg; 982455SN/A typedef TheISA::FloatReg FloatReg; 992455SN/A typedef TheISA::FloatRegBits FloatRegBits; 1009920Syasuko.eckert@amd.com typedef TheISA::CCReg CCReg; 1012159SN/A typedef TheISA::MiscReg MiscReg; 1022SN/A public: 1036029Ssteve.reinhardt@amd.com 104246SN/A enum Status 105246SN/A { 106246SN/A /// Running. Instructions should be executed only when 107246SN/A /// the context is in this state. 108246SN/A Active, 109246SN/A 110246SN/A /// Temporarily inactive. Entered while waiting for 1112190SN/A /// synchronization, etc. 112246SN/A Suspended, 113246SN/A 114246SN/A /// Permanently shut down. Entered when target executes 115246SN/A /// m5exit pseudo-instruction. When all contexts enter 116246SN/A /// this state, the simulation will terminate. 117246SN/A Halted 118246SN/A }; 1192SN/A 1202680Sktlim@umich.edu virtual ~ThreadContext() { }; 1212423SN/A 1222190SN/A virtual BaseCPU *getCpuPtr() = 0; 123180SN/A 12410110Sandreas.hansson@arm.com virtual int cpuId() const = 0; 1252190SN/A 12610190Sakash.bagdia@arm.com virtual uint32_t socketId() const = 0; 12710190Sakash.bagdia@arm.com 12810110Sandreas.hansson@arm.com virtual int threadId() const = 0; 1295715Shsul@eecs.umich.edu 1305715Shsul@eecs.umich.edu virtual void setThreadId(int id) = 0; 1315714Shsul@eecs.umich.edu 13210110Sandreas.hansson@arm.com virtual int contextId() const = 0; 1335714Shsul@eecs.umich.edu 1345714Shsul@eecs.umich.edu virtual void setContextId(int id) = 0; 1355714Shsul@eecs.umich.edu 1366022Sgblack@eecs.umich.edu virtual TheISA::TLB *getITBPtr() = 0; 1372190SN/A 1386022Sgblack@eecs.umich.edu virtual TheISA::TLB *getDTBPtr() = 0; 1392521SN/A 1408887Sgeoffrey.blake@arm.com virtual CheckerCPU *getCheckerCpuPtr() = 0; 1418733Sgeoffrey.blake@arm.com 1429020Sgblack@eecs.umich.edu virtual TheISA::Decoder *getDecoderPtr() = 0; 1438541Sgblack@eecs.umich.edu 1444997Sgblack@eecs.umich.edu virtual System *getSystemPtr() = 0; 1454997Sgblack@eecs.umich.edu 1463548Sgblack@eecs.umich.edu virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 1472654SN/A 1488852Sandreas.hansson@arm.com virtual PortProxy &getPhysProxy() = 0; 1492521SN/A 1508852Sandreas.hansson@arm.com virtual FSTranslatingPortProxy &getVirtProxy() = 0; 1513673Srdreslin@umich.edu 1528706Sandreas.hansson@arm.com /** 1538706Sandreas.hansson@arm.com * Initialise the physical and virtual port proxies and tie them to 1548706Sandreas.hansson@arm.com * the data port of the CPU. 1558706Sandreas.hansson@arm.com * 1568706Sandreas.hansson@arm.com * tc ThreadContext for the virtual-to-physical translation 1578706Sandreas.hansson@arm.com */ 1588706Sandreas.hansson@arm.com virtual void initMemProxies(ThreadContext *tc) = 0; 1598799Sgblack@eecs.umich.edu 1608852Sandreas.hansson@arm.com virtual SETranslatingPortProxy &getMemProxy() = 0; 1612518SN/A 1622190SN/A virtual Process *getProcessPtr() = 0; 1632190SN/A 1642190SN/A virtual Status status() const = 0; 1652159SN/A 1662235SN/A virtual void setStatus(Status new_status) = 0; 1672103SN/A 168393SN/A /// Set the status to Active. Optional delay indicates number of 169393SN/A /// cycles to wait before beginning execution. 1709180Sandreas.hansson@arm.com virtual void activate(Cycles delay = Cycles(1)) = 0; 171393SN/A 172393SN/A /// Set the status to Suspended. 1739180Sandreas.hansson@arm.com virtual void suspend(Cycles delay = Cycles(0)) = 0; 174393SN/A 175393SN/A /// Set the status to Halted. 1769180Sandreas.hansson@arm.com virtual void halt(Cycles delay = Cycles(0)) = 0; 1772159SN/A 1782190SN/A virtual void dumpFuncProfile() = 0; 1792159SN/A 1802680Sktlim@umich.edu virtual void takeOverFrom(ThreadContext *old_context) = 0; 1812159SN/A 1822190SN/A virtual void regStats(const std::string &name) = 0; 1832159SN/A 1842313SN/A virtual EndQuiesceEvent *getQuiesceEvent() = 0; 1852235SN/A 1862235SN/A // Not necessarily the best location for these... 1872235SN/A // Having an extra function just to read these is obnoxious 1882235SN/A virtual Tick readLastActivate() = 0; 1892235SN/A virtual Tick readLastSuspend() = 0; 1902254SN/A 1912254SN/A virtual void profileClear() = 0; 1922254SN/A virtual void profileSample() = 0; 1932235SN/A 1942680Sktlim@umich.edu virtual void copyArchRegs(ThreadContext *tc) = 0; 1952159SN/A 1962190SN/A virtual void clearArchRegs() = 0; 1972159SN/A 1982159SN/A // 1992159SN/A // New accessors for new decoder. 2002159SN/A // 2012190SN/A virtual uint64_t readIntReg(int reg_idx) = 0; 2022159SN/A 2032455SN/A virtual FloatReg readFloatReg(int reg_idx) = 0; 2042159SN/A 2052455SN/A virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 2062159SN/A 2079920Syasuko.eckert@amd.com virtual CCReg readCCReg(int reg_idx) = 0; 2089920Syasuko.eckert@amd.com 2092190SN/A virtual void setIntReg(int reg_idx, uint64_t val) = 0; 2102159SN/A 2112455SN/A virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 2122159SN/A 2132455SN/A virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 2142455SN/A 2159920Syasuko.eckert@amd.com virtual void setCCReg(int reg_idx, CCReg val) = 0; 2169920Syasuko.eckert@amd.com 2177720Sgblack@eecs.umich.edu virtual TheISA::PCState pcState() = 0; 2182159SN/A 2197720Sgblack@eecs.umich.edu virtual void pcState(const TheISA::PCState &val) = 0; 2202159SN/A 2218733Sgeoffrey.blake@arm.com virtual void pcStateNoRecord(const TheISA::PCState &val) = 0; 2228733Sgeoffrey.blake@arm.com 2237720Sgblack@eecs.umich.edu virtual Addr instAddr() = 0; 2242159SN/A 2257720Sgblack@eecs.umich.edu virtual Addr nextInstAddr() = 0; 2262159SN/A 2277720Sgblack@eecs.umich.edu virtual MicroPC microPC() = 0; 2285260Sksewell@umich.edu 2294172Ssaidi@eecs.umich.edu virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; 2304172Ssaidi@eecs.umich.edu 2312190SN/A virtual MiscReg readMiscReg(int misc_reg) = 0; 2322159SN/A 2334172Ssaidi@eecs.umich.edu virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; 2342190SN/A 2353468Sgblack@eecs.umich.edu virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 2362190SN/A 2376313Sgblack@eecs.umich.edu virtual int flattenIntIndex(int reg) = 0; 2386313Sgblack@eecs.umich.edu virtual int flattenFloatIndex(int reg) = 0; 2399920Syasuko.eckert@amd.com virtual int flattenCCIndex(int reg) = 0; 24010033SAli.Saidi@ARM.com virtual int flattenMiscIndex(int reg) = 0; 2416313Sgblack@eecs.umich.edu 2426221Snate@binkert.org virtual uint64_t 2436221Snate@binkert.org readRegOtherThread(int misc_reg, ThreadID tid) 2446221Snate@binkert.org { 2456221Snate@binkert.org return 0; 2466221Snate@binkert.org } 2474661Sksewell@umich.edu 2486221Snate@binkert.org virtual void 2496221Snate@binkert.org setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid) 2506221Snate@binkert.org { 2516221Snate@binkert.org } 2524661Sksewell@umich.edu 2532235SN/A // Also not necessarily the best location for these two. Hopefully will go 2542235SN/A // away once we decide upon where st cond failures goes. 2552190SN/A virtual unsigned readStCondFailures() = 0; 2562190SN/A 2572190SN/A virtual void setStCondFailures(unsigned sc_failures) = 0; 2582159SN/A 2592235SN/A // Only really makes sense for old CPU model. Still could be useful though. 2602190SN/A virtual bool misspeculating() = 0; 2612190SN/A 2622235SN/A // Same with st cond failures. 2632190SN/A virtual Counter readFuncExeInst() = 0; 2642834Sksewell@umich.edu 2654111Sgblack@eecs.umich.edu virtual void syscall(int64_t callnum) = 0; 2664111Sgblack@eecs.umich.edu 2672834Sksewell@umich.edu // This function exits the thread context in the CPU and returns 2682834Sksewell@umich.edu // 1 if the CPU has no more active threads (meaning it's OK to exit); 2692834Sksewell@umich.edu // Used in syscall-emulation mode when a thread calls the exit syscall. 2702834Sksewell@umich.edu virtual int exit() { return 1; }; 2712525SN/A 2725217Ssaidi@eecs.umich.edu /** function to compare two thread contexts (for debugging) */ 2735217Ssaidi@eecs.umich.edu static void compare(ThreadContext *one, ThreadContext *two); 2749426SAndreas.Sandberg@ARM.com 2759426SAndreas.Sandberg@ARM.com /** @{ */ 2769426SAndreas.Sandberg@ARM.com /** 2779426SAndreas.Sandberg@ARM.com * Flat register interfaces 2789426SAndreas.Sandberg@ARM.com * 2799426SAndreas.Sandberg@ARM.com * Some architectures have different registers visible in 2809426SAndreas.Sandberg@ARM.com * different modes. Such architectures "flatten" a register (see 2819426SAndreas.Sandberg@ARM.com * flattenIntIndex() and flattenFloatIndex()) to map it into the 2829426SAndreas.Sandberg@ARM.com * gem5 register file. This interface provides a flat interface to 2839426SAndreas.Sandberg@ARM.com * the underlying register file, which allows for example 2849426SAndreas.Sandberg@ARM.com * serialization code to access all registers. 2859426SAndreas.Sandberg@ARM.com */ 2869426SAndreas.Sandberg@ARM.com 2879426SAndreas.Sandberg@ARM.com virtual uint64_t readIntRegFlat(int idx) = 0; 2889426SAndreas.Sandberg@ARM.com virtual void setIntRegFlat(int idx, uint64_t val) = 0; 2899426SAndreas.Sandberg@ARM.com 2909426SAndreas.Sandberg@ARM.com virtual FloatReg readFloatRegFlat(int idx) = 0; 2919426SAndreas.Sandberg@ARM.com virtual void setFloatRegFlat(int idx, FloatReg val) = 0; 2929426SAndreas.Sandberg@ARM.com 2939426SAndreas.Sandberg@ARM.com virtual FloatRegBits readFloatRegBitsFlat(int idx) = 0; 2949426SAndreas.Sandberg@ARM.com virtual void setFloatRegBitsFlat(int idx, FloatRegBits val) = 0; 2959426SAndreas.Sandberg@ARM.com 2969920Syasuko.eckert@amd.com virtual CCReg readCCRegFlat(int idx) = 0; 2979920Syasuko.eckert@amd.com virtual void setCCRegFlat(int idx, CCReg val) = 0; 2989426SAndreas.Sandberg@ARM.com /** @} */ 2999426SAndreas.Sandberg@ARM.com 3002159SN/A}; 3012159SN/A 3022682Sktlim@umich.edu/** 3032682Sktlim@umich.edu * ProxyThreadContext class that provides a way to implement a 3042682Sktlim@umich.edu * ThreadContext without having to derive from it. ThreadContext is an 3052682Sktlim@umich.edu * abstract class, so anything that derives from it and uses its 3062682Sktlim@umich.edu * interface will pay the overhead of virtual function calls. This 3072682Sktlim@umich.edu * class is created to enable a user-defined Thread object to be used 3082682Sktlim@umich.edu * wherever ThreadContexts are used, without paying the overhead of 3092682Sktlim@umich.edu * virtual function calls when it is used by itself. See 3102682Sktlim@umich.edu * simple_thread.hh for an example of this. 3112682Sktlim@umich.edu */ 3122680Sktlim@umich.edutemplate <class TC> 3132680Sktlim@umich.educlass ProxyThreadContext : public ThreadContext 3142190SN/A{ 3152190SN/A public: 3162680Sktlim@umich.edu ProxyThreadContext(TC *actual_tc) 3172680Sktlim@umich.edu { actualTC = actual_tc; } 3182159SN/A 3192190SN/A private: 3202680Sktlim@umich.edu TC *actualTC; 3212SN/A 3222SN/A public: 3232SN/A 3242680Sktlim@umich.edu BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 3252SN/A 32610110Sandreas.hansson@arm.com int cpuId() const { return actualTC->cpuId(); } 3272SN/A 32810190Sakash.bagdia@arm.com uint32_t socketId() const { return actualTC->socketId(); } 32910190Sakash.bagdia@arm.com 33010110Sandreas.hansson@arm.com int threadId() const { return actualTC->threadId(); } 3315715Shsul@eecs.umich.edu 33210110Sandreas.hansson@arm.com void setThreadId(int id) { actualTC->setThreadId(id); } 3335714Shsul@eecs.umich.edu 33410110Sandreas.hansson@arm.com int contextId() const { return actualTC->contextId(); } 3355714Shsul@eecs.umich.edu 3365714Shsul@eecs.umich.edu void setContextId(int id) { actualTC->setContextId(id); } 3375714Shsul@eecs.umich.edu 3386022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 3391917SN/A 3406022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 3412521SN/A 3428887Sgeoffrey.blake@arm.com CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); } 3438733Sgeoffrey.blake@arm.com 3449020Sgblack@eecs.umich.edu TheISA::Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); } 3458541Sgblack@eecs.umich.edu 3464997Sgblack@eecs.umich.edu System *getSystemPtr() { return actualTC->getSystemPtr(); } 3474997Sgblack@eecs.umich.edu 3483548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *getKernelStats() 3493548Sgblack@eecs.umich.edu { return actualTC->getKernelStats(); } 3502654SN/A 3518852Sandreas.hansson@arm.com PortProxy &getPhysProxy() { return actualTC->getPhysProxy(); } 3522521SN/A 3538852Sandreas.hansson@arm.com FSTranslatingPortProxy &getVirtProxy() { return actualTC->getVirtProxy(); } 3543673Srdreslin@umich.edu 3558706Sandreas.hansson@arm.com void initMemProxies(ThreadContext *tc) { actualTC->initMemProxies(tc); } 3568799Sgblack@eecs.umich.edu 3578852Sandreas.hansson@arm.com SETranslatingPortProxy &getMemProxy() { return actualTC->getMemProxy(); } 3582518SN/A 3592680Sktlim@umich.edu Process *getProcessPtr() { return actualTC->getProcessPtr(); } 3602SN/A 3612680Sktlim@umich.edu Status status() const { return actualTC->status(); } 362595SN/A 3632680Sktlim@umich.edu void setStatus(Status new_status) { actualTC->setStatus(new_status); } 3642SN/A 3652190SN/A /// Set the status to Active. Optional delay indicates number of 3662190SN/A /// cycles to wait before beginning execution. 3679180Sandreas.hansson@arm.com void activate(Cycles delay = Cycles(1)) 3689180Sandreas.hansson@arm.com { actualTC->activate(delay); } 3692SN/A 3702190SN/A /// Set the status to Suspended. 3719180Sandreas.hansson@arm.com void suspend(Cycles delay = Cycles(0)) { actualTC->suspend(); } 3722SN/A 3732190SN/A /// Set the status to Halted. 3749180Sandreas.hansson@arm.com void halt(Cycles delay = Cycles(0)) { actualTC->halt(); } 375217SN/A 3762680Sktlim@umich.edu void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 3772190SN/A 3782680Sktlim@umich.edu void takeOverFrom(ThreadContext *oldContext) 3792680Sktlim@umich.edu { actualTC->takeOverFrom(oldContext); } 3802190SN/A 3812680Sktlim@umich.edu void regStats(const std::string &name) { actualTC->regStats(name); } 3822190SN/A 3832680Sktlim@umich.edu EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 3842235SN/A 3852680Sktlim@umich.edu Tick readLastActivate() { return actualTC->readLastActivate(); } 3862680Sktlim@umich.edu Tick readLastSuspend() { return actualTC->readLastSuspend(); } 3872254SN/A 3882680Sktlim@umich.edu void profileClear() { return actualTC->profileClear(); } 3892680Sktlim@umich.edu void profileSample() { return actualTC->profileSample(); } 3902SN/A 3912190SN/A // @todo: Do I need this? 3922680Sktlim@umich.edu void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 3932SN/A 3942680Sktlim@umich.edu void clearArchRegs() { actualTC->clearArchRegs(); } 395716SN/A 3962SN/A // 3972SN/A // New accessors for new decoder. 3982SN/A // 3992SN/A uint64_t readIntReg(int reg_idx) 4002680Sktlim@umich.edu { return actualTC->readIntReg(reg_idx); } 4012SN/A 4022455SN/A FloatReg readFloatReg(int reg_idx) 4032680Sktlim@umich.edu { return actualTC->readFloatReg(reg_idx); } 4042SN/A 4052455SN/A FloatRegBits readFloatRegBits(int reg_idx) 4062680Sktlim@umich.edu { return actualTC->readFloatRegBits(reg_idx); } 4072SN/A 4089920Syasuko.eckert@amd.com CCReg readCCReg(int reg_idx) 4099920Syasuko.eckert@amd.com { return actualTC->readCCReg(reg_idx); } 4109920Syasuko.eckert@amd.com 4112SN/A void setIntReg(int reg_idx, uint64_t val) 4122680Sktlim@umich.edu { actualTC->setIntReg(reg_idx, val); } 4132SN/A 4142455SN/A void setFloatReg(int reg_idx, FloatReg val) 4152680Sktlim@umich.edu { actualTC->setFloatReg(reg_idx, val); } 4162SN/A 4172455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 4182680Sktlim@umich.edu { actualTC->setFloatRegBits(reg_idx, val); } 4192SN/A 4209920Syasuko.eckert@amd.com void setCCReg(int reg_idx, CCReg val) 4219920Syasuko.eckert@amd.com { actualTC->setCCReg(reg_idx, val); } 4229920Syasuko.eckert@amd.com 4237720Sgblack@eecs.umich.edu TheISA::PCState pcState() { return actualTC->pcState(); } 4242SN/A 4257720Sgblack@eecs.umich.edu void pcState(const TheISA::PCState &val) { actualTC->pcState(val); } 4262206SN/A 4278733Sgeoffrey.blake@arm.com void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); } 4288733Sgeoffrey.blake@arm.com 4297720Sgblack@eecs.umich.edu Addr instAddr() { return actualTC->instAddr(); } 4307720Sgblack@eecs.umich.edu Addr nextInstAddr() { return actualTC->nextInstAddr(); } 4317720Sgblack@eecs.umich.edu MicroPC microPC() { return actualTC->microPC(); } 4325260Sksewell@umich.edu 4337597Sminkyu.jeong@arm.com bool readPredicate() { return actualTC->readPredicate(); } 4347597Sminkyu.jeong@arm.com 4357597Sminkyu.jeong@arm.com void setPredicate(bool val) 4367597Sminkyu.jeong@arm.com { actualTC->setPredicate(val); } 4377597Sminkyu.jeong@arm.com 4384172Ssaidi@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg) 4394172Ssaidi@eecs.umich.edu { return actualTC->readMiscRegNoEffect(misc_reg); } 4404172Ssaidi@eecs.umich.edu 4412159SN/A MiscReg readMiscReg(int misc_reg) 4422680Sktlim@umich.edu { return actualTC->readMiscReg(misc_reg); } 4432SN/A 4444172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 4454172Ssaidi@eecs.umich.edu { return actualTC->setMiscRegNoEffect(misc_reg, val); } 4462SN/A 4473468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 4482680Sktlim@umich.edu { return actualTC->setMiscReg(misc_reg, val); } 4492SN/A 4506313Sgblack@eecs.umich.edu int flattenIntIndex(int reg) 4516313Sgblack@eecs.umich.edu { return actualTC->flattenIntIndex(reg); } 4526313Sgblack@eecs.umich.edu 4536313Sgblack@eecs.umich.edu int flattenFloatIndex(int reg) 4546313Sgblack@eecs.umich.edu { return actualTC->flattenFloatIndex(reg); } 4556313Sgblack@eecs.umich.edu 4569920Syasuko.eckert@amd.com int flattenCCIndex(int reg) 4579920Syasuko.eckert@amd.com { return actualTC->flattenCCIndex(reg); } 4589920Syasuko.eckert@amd.com 45910033SAli.Saidi@ARM.com int flattenMiscIndex(int reg) 46010033SAli.Saidi@ARM.com { return actualTC->flattenMiscIndex(reg); } 46110033SAli.Saidi@ARM.com 4622190SN/A unsigned readStCondFailures() 4632680Sktlim@umich.edu { return actualTC->readStCondFailures(); } 4642190SN/A 4652190SN/A void setStCondFailures(unsigned sc_failures) 4662680Sktlim@umich.edu { actualTC->setStCondFailures(sc_failures); } 4672SN/A 4682190SN/A // @todo: Fix this! 4692680Sktlim@umich.edu bool misspeculating() { return actualTC->misspeculating(); } 4702190SN/A 4714111Sgblack@eecs.umich.edu void syscall(int64_t callnum) 4724111Sgblack@eecs.umich.edu { actualTC->syscall(callnum); } 4734111Sgblack@eecs.umich.edu 4742680Sktlim@umich.edu Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 4759426SAndreas.Sandberg@ARM.com 4769426SAndreas.Sandberg@ARM.com uint64_t readIntRegFlat(int idx) 4779426SAndreas.Sandberg@ARM.com { return actualTC->readIntRegFlat(idx); } 4789426SAndreas.Sandberg@ARM.com 4799426SAndreas.Sandberg@ARM.com void setIntRegFlat(int idx, uint64_t val) 4809426SAndreas.Sandberg@ARM.com { actualTC->setIntRegFlat(idx, val); } 4819426SAndreas.Sandberg@ARM.com 4829426SAndreas.Sandberg@ARM.com FloatReg readFloatRegFlat(int idx) 4839426SAndreas.Sandberg@ARM.com { return actualTC->readFloatRegFlat(idx); } 4849426SAndreas.Sandberg@ARM.com 4859426SAndreas.Sandberg@ARM.com void setFloatRegFlat(int idx, FloatReg val) 4869426SAndreas.Sandberg@ARM.com { actualTC->setFloatRegFlat(idx, val); } 4879426SAndreas.Sandberg@ARM.com 4889426SAndreas.Sandberg@ARM.com FloatRegBits readFloatRegBitsFlat(int idx) 4899426SAndreas.Sandberg@ARM.com { return actualTC->readFloatRegBitsFlat(idx); } 4909426SAndreas.Sandberg@ARM.com 4919426SAndreas.Sandberg@ARM.com void setFloatRegBitsFlat(int idx, FloatRegBits val) 4929426SAndreas.Sandberg@ARM.com { actualTC->setFloatRegBitsFlat(idx, val); } 4939920Syasuko.eckert@amd.com 4949920Syasuko.eckert@amd.com CCReg readCCRegFlat(int idx) 4959920Syasuko.eckert@amd.com { return actualTC->readCCRegFlat(idx); } 4969920Syasuko.eckert@amd.com 4979920Syasuko.eckert@amd.com void setCCRegFlat(int idx, CCReg val) 4989920Syasuko.eckert@amd.com { actualTC->setCCRegFlat(idx, val); } 4992SN/A}; 5002SN/A 5019428SAndreas.Sandberg@ARM.com/** @{ */ 5029428SAndreas.Sandberg@ARM.com/** 5039428SAndreas.Sandberg@ARM.com * Thread context serialization helpers 5049428SAndreas.Sandberg@ARM.com * 5059428SAndreas.Sandberg@ARM.com * These helper functions provide a way to the data in a 5069428SAndreas.Sandberg@ARM.com * ThreadContext. They are provided as separate helper function since 5079428SAndreas.Sandberg@ARM.com * implementing them as members of the ThreadContext interface would 5089428SAndreas.Sandberg@ARM.com * be confusing when the ThreadContext is exported via a proxy. 5099428SAndreas.Sandberg@ARM.com */ 5109428SAndreas.Sandberg@ARM.com 5119428SAndreas.Sandberg@ARM.comvoid serialize(ThreadContext &tc, std::ostream &os); 5129428SAndreas.Sandberg@ARM.comvoid unserialize(ThreadContext &tc, Checkpoint *cp, const std::string §ion); 5139428SAndreas.Sandberg@ARM.com 5149428SAndreas.Sandberg@ARM.com/** @} */ 5159428SAndreas.Sandberg@ARM.com 5169441SAndreas.Sandberg@ARM.com 5179441SAndreas.Sandberg@ARM.com/** 5189441SAndreas.Sandberg@ARM.com * Copy state between thread contexts in preparation for CPU handover. 5199441SAndreas.Sandberg@ARM.com * 5209441SAndreas.Sandberg@ARM.com * @note This method modifies the old thread contexts as well as the 5219441SAndreas.Sandberg@ARM.com * new thread context. The old thread context will have its quiesce 5229441SAndreas.Sandberg@ARM.com * event descheduled if it is scheduled and its status set to halted. 5239441SAndreas.Sandberg@ARM.com * 5249441SAndreas.Sandberg@ARM.com * @param new_tc Destination ThreadContext. 5259441SAndreas.Sandberg@ARM.com * @param old_tc Source ThreadContext. 5269441SAndreas.Sandberg@ARM.com */ 5279441SAndreas.Sandberg@ARM.comvoid takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc); 5289441SAndreas.Sandberg@ARM.com 5292190SN/A#endif 530