thread_context.cc revision 9441:1133617844c8
14776Sgblack@eecs.umich.edu/* 24776Sgblack@eecs.umich.edu * Copyright (c) 2012 ARM Limited 34776Sgblack@eecs.umich.edu * All rights reserved 44776Sgblack@eecs.umich.edu * 54776Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 64776Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 74776Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 84776Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 94776Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 104776Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 114776Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 124776Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 134776Sgblack@eecs.umich.edu * 144776Sgblack@eecs.umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 154776Sgblack@eecs.umich.edu * All rights reserved. 164776Sgblack@eecs.umich.edu * 174776Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 184776Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 194776Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 204776Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 214776Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 224776Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 234776Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 244776Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 254776Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 264776Sgblack@eecs.umich.edu * this software without specific prior written permission. 274776Sgblack@eecs.umich.edu * 284776Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 294776Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 304776Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 314776Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326216Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336216Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 344776Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 354776Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366216Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 374776Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 385034Smilesck@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 394776Sgblack@eecs.umich.edu * 404776Sgblack@eecs.umich.edu * Authors: Kevin Lim 414776Sgblack@eecs.umich.edu */ 424776Sgblack@eecs.umich.edu 434776Sgblack@eecs.umich.edu#include "base/misc.hh" 444776Sgblack@eecs.umich.edu#include "base/trace.hh" 454776Sgblack@eecs.umich.edu#include "config/the_isa.hh" 464776Sgblack@eecs.umich.edu#include "cpu/base.hh" 474776Sgblack@eecs.umich.edu#include "cpu/quiesce_event.hh" 484776Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 497720Sgblack@eecs.umich.edu#include "debug/Context.hh" 507720Sgblack@eecs.umich.edu#include "sim/full_system.hh" 515784Sgblack@eecs.umich.edu 527720Sgblack@eecs.umich.eduvoid 534776Sgblack@eecs.umich.eduThreadContext::compare(ThreadContext *one, ThreadContext *two) 544776Sgblack@eecs.umich.edu{ 554776Sgblack@eecs.umich.edu DPRINTF(Context, "Comparing thread contexts\n"); 564776Sgblack@eecs.umich.edu 574776Sgblack@eecs.umich.edu // First loop through the integer registers. 584776Sgblack@eecs.umich.edu for (int i = 0; i < TheISA::NumIntRegs; ++i) { 594776Sgblack@eecs.umich.edu TheISA::IntReg t1 = one->readIntReg(i); 604776Sgblack@eecs.umich.edu TheISA::IntReg t2 = two->readIntReg(i); 614776Sgblack@eecs.umich.edu if (t1 != t2) 624776Sgblack@eecs.umich.edu panic("Int reg idx %d doesn't match, one: %#x, two: %#x", 635034Smilesck@eecs.umich.edu i, t1, t2); 644776Sgblack@eecs.umich.edu } 654776Sgblack@eecs.umich.edu 664776Sgblack@eecs.umich.edu // Then loop through the floating point registers. 674776Sgblack@eecs.umich.edu for (int i = 0; i < TheISA::NumFloatRegs; ++i) { 687720Sgblack@eecs.umich.edu TheISA::FloatRegBits t1 = one->readFloatRegBits(i); 697720Sgblack@eecs.umich.edu TheISA::FloatRegBits t2 = two->readFloatRegBits(i); 704776Sgblack@eecs.umich.edu if (t1 != t2) 714776Sgblack@eecs.umich.edu panic("Float reg idx %d doesn't match, one: %#x, two: %#x", 724776Sgblack@eecs.umich.edu i, t1, t2); 734776Sgblack@eecs.umich.edu } 744776Sgblack@eecs.umich.edu for (int i = 0; i < TheISA::NumMiscRegs; ++i) { 754776Sgblack@eecs.umich.edu TheISA::MiscReg t1 = one->readMiscRegNoEffect(i); 764776Sgblack@eecs.umich.edu TheISA::MiscReg t2 = two->readMiscRegNoEffect(i); 774776Sgblack@eecs.umich.edu if (t1 != t2) 784776Sgblack@eecs.umich.edu panic("Misc reg idx %d doesn't match, one: %#x, two: %#x", 794776Sgblack@eecs.umich.edu i, t1, t2); 804776Sgblack@eecs.umich.edu } 817720Sgblack@eecs.umich.edu 824776Sgblack@eecs.umich.edu if (!(one->pcState() == two->pcState())) 834776Sgblack@eecs.umich.edu panic("PC state doesn't match."); 844776Sgblack@eecs.umich.edu int id1 = one->cpuId(); 854776Sgblack@eecs.umich.edu int id2 = two->cpuId(); 864776Sgblack@eecs.umich.edu if (id1 != id2) 876216Snate@binkert.org panic("CPU ids don't match, one: %d, two: %d", id1, id2); 88 89 id1 = one->contextId(); 90 id2 = two->contextId(); 91 if (id1 != id2) 92 panic("Context ids don't match, one: %d, two: %d", id1, id2); 93 94 95} 96 97void 98serialize(ThreadContext &tc, std::ostream &os) 99{ 100 using namespace TheISA; 101 102 FloatRegBits floatRegs[NumFloatRegs]; 103 for (int i = 0; i < NumFloatRegs; ++i) 104 floatRegs[i] = tc.readFloatRegBitsFlat(i); 105 // This is a bit ugly, but needed to maintain backwards 106 // compatibility. 107 arrayParamOut(os, "floatRegs.i", floatRegs, NumFloatRegs); 108 109 IntReg intRegs[NumIntRegs]; 110 for (int i = 0; i < NumIntRegs; ++i) 111 intRegs[i] = tc.readIntRegFlat(i); 112 SERIALIZE_ARRAY(intRegs, NumIntRegs); 113 114 tc.pcState().serialize(os); 115 116 // thread_num and cpu_id are deterministic from the config 117} 118 119void 120unserialize(ThreadContext &tc, Checkpoint *cp, const std::string §ion) 121{ 122 using namespace TheISA; 123 124 FloatRegBits floatRegs[NumFloatRegs]; 125 // This is a bit ugly, but needed to maintain backwards 126 // compatibility. 127 arrayParamIn(cp, section, "floatRegs.i", floatRegs, NumFloatRegs); 128 for (int i = 0; i < NumFloatRegs; ++i) 129 tc.setFloatRegBitsFlat(i, floatRegs[i]); 130 131 IntReg intRegs[NumIntRegs]; 132 UNSERIALIZE_ARRAY(intRegs, NumIntRegs); 133 for (int i = 0; i < NumIntRegs; ++i) 134 tc.setIntRegFlat(i, intRegs[i]); 135 136 PCState pcState; 137 pcState.unserialize(cp, section); 138 tc.pcState(pcState); 139 140 // thread_num and cpu_id are deterministic from the config 141} 142 143void 144takeOverFrom(ThreadContext &ntc, ThreadContext &otc) 145{ 146 assert(ntc.getProcessPtr() == otc.getProcessPtr()); 147 148 ntc.setStatus(otc.status()); 149 ntc.copyArchRegs(&otc); 150 ntc.setContextId(otc.contextId()); 151 ntc.setThreadId(otc.threadId()); 152 153 if (FullSystem) { 154 assert(ntc.getSystemPtr() == otc.getSystemPtr()); 155 156 BaseCPU *ncpu(ntc.getCpuPtr()); 157 assert(ncpu); 158 EndQuiesceEvent *oqe(otc.getQuiesceEvent()); 159 assert(oqe); 160 assert(oqe->tc == &otc); 161 162 BaseCPU *ocpu(otc.getCpuPtr()); 163 assert(ocpu); 164 EndQuiesceEvent *nqe(ntc.getQuiesceEvent()); 165 assert(nqe); 166 assert(nqe->tc == &ntc); 167 168 if (oqe->scheduled()) { 169 ncpu->schedule(nqe, oqe->when()); 170 ocpu->deschedule(oqe); 171 } 172 } 173 174 otc.setStatus(ThreadContext::Halted); 175} 176