thread_context.cc revision 9441
13804SN/A/* 212776Snikos.nikoleris@arm.com * Copyright (c) 2012 ARM Limited 39235Sandreas.hansson@arm.com * All rights reserved 49235Sandreas.hansson@arm.com * 59235Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 69235Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 79235Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 89235Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 99235Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 109235Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 119235Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 129235Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 139235Sandreas.hansson@arm.com * 143804SN/A * Copyright (c) 2006 The Regents of The University of Michigan 153804SN/A * All rights reserved. 163804SN/A * 173804SN/A * Redistribution and use in source and binary forms, with or without 183804SN/A * modification, are permitted provided that the following conditions are 193804SN/A * met: redistributions of source code must retain the above copyright 203804SN/A * notice, this list of conditions and the following disclaimer; 213804SN/A * redistributions in binary form must reproduce the above copyright 223804SN/A * notice, this list of conditions and the following disclaimer in the 233804SN/A * documentation and/or other materials provided with the distribution; 243804SN/A * neither the name of the copyright holders nor the names of its 253804SN/A * contributors may be used to endorse or promote products derived from 263804SN/A * this software without specific prior written permission. 273804SN/A * 283804SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 293804SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 303804SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 313804SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 323804SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 333804SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 343804SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 353804SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 363804SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 373804SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 383804SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 393804SN/A * 403804SN/A * Authors: Kevin Lim 419235Sandreas.hansson@arm.com */ 423804SN/A 433804SN/A#include "base/misc.hh" 449235Sandreas.hansson@arm.com#include "base/trace.hh" 459235Sandreas.hansson@arm.com#include "config/the_isa.hh" 463804SN/A#include "cpu/base.hh" 478229SN/A#include "cpu/quiesce_event.hh" 488902SN/A#include "cpu/thread_context.hh" 498229SN/A#include "debug/Context.hh" 509235Sandreas.hansson@arm.com#include "sim/full_system.hh" 513804SN/A 528918SN/Avoid 539235Sandreas.hansson@arm.comThreadContext::compare(ThreadContext *one, ThreadContext *two) 549235Sandreas.hansson@arm.com{ 559235Sandreas.hansson@arm.com DPRINTF(Context, "Comparing thread contexts\n"); 568918SN/A 5712777Sgabeblack@google.com // First loop through the integer registers. 589235Sandreas.hansson@arm.com for (int i = 0; i < TheISA::NumIntRegs; ++i) { 593804SN/A TheISA::IntReg t1 = one->readIntReg(i); 603804SN/A TheISA::IntReg t2 = two->readIntReg(i); 619235Sandreas.hansson@arm.com if (t1 != t2) 623804SN/A panic("Int reg idx %d doesn't match, one: %#x, two: %#x", 633804SN/A i, t1, t2); 643804SN/A } 658918SN/A 663804SN/A // Then loop through the floating point registers. 6712776Snikos.nikoleris@arm.com for (int i = 0; i < TheISA::NumFloatRegs; ++i) { 6812776Snikos.nikoleris@arm.com TheISA::FloatRegBits t1 = one->readFloatRegBits(i); 6912776Snikos.nikoleris@arm.com TheISA::FloatRegBits t2 = two->readFloatRegBits(i); 7012776Snikos.nikoleris@arm.com if (t1 != t2) 7112776Snikos.nikoleris@arm.com panic("Float reg idx %d doesn't match, one: %#x, two: %#x", 7212776Snikos.nikoleris@arm.com i, t1, t2); 7312776Snikos.nikoleris@arm.com } 7412776Snikos.nikoleris@arm.com for (int i = 0; i < TheISA::NumMiscRegs; ++i) { 7512776Snikos.nikoleris@arm.com TheISA::MiscReg t1 = one->readMiscRegNoEffect(i); 7612776Snikos.nikoleris@arm.com TheISA::MiscReg t2 = two->readMiscRegNoEffect(i); 778918SN/A if (t1 != t2) 7812776Snikos.nikoleris@arm.com panic("Misc reg idx %d doesn't match, one: %#x, two: %#x", 798918SN/A i, t1, t2); 8012776Snikos.nikoleris@arm.com } 813804SN/A 823804SN/A if (!(one->pcState() == two->pcState())) 8312776Snikos.nikoleris@arm.com panic("PC state doesn't match."); 8412776Snikos.nikoleris@arm.com int id1 = one->cpuId(); 8512776Snikos.nikoleris@arm.com int id2 = two->cpuId(); 8612776Snikos.nikoleris@arm.com if (id1 != id2) 8712776Snikos.nikoleris@arm.com panic("CPU ids don't match, one: %d, two: %d", id1, id2); 8812776Snikos.nikoleris@arm.com 8912776Snikos.nikoleris@arm.com id1 = one->contextId(); 9012776Snikos.nikoleris@arm.com id2 = two->contextId(); 9112776Snikos.nikoleris@arm.com if (id1 != id2) 9212776Snikos.nikoleris@arm.com panic("Context ids don't match, one: %d, two: %d", id1, id2); 938918SN/A 9412776Snikos.nikoleris@arm.com 958918SN/A} 9612776Snikos.nikoleris@arm.com 978918SN/Avoid 988918SN/Aserialize(ThreadContext &tc, std::ostream &os) 9912776Snikos.nikoleris@arm.com{ 10012776Snikos.nikoleris@arm.com using namespace TheISA; 10112776Snikos.nikoleris@arm.com 10212776Snikos.nikoleris@arm.com FloatRegBits floatRegs[NumFloatRegs]; 10312776Snikos.nikoleris@arm.com for (int i = 0; i < NumFloatRegs; ++i) 10412776Snikos.nikoleris@arm.com floatRegs[i] = tc.readFloatRegBitsFlat(i); 10512776Snikos.nikoleris@arm.com // This is a bit ugly, but needed to maintain backwards 10612776Snikos.nikoleris@arm.com // compatibility. 10712776Snikos.nikoleris@arm.com arrayParamOut(os, "floatRegs.i", floatRegs, NumFloatRegs); 10812776Snikos.nikoleris@arm.com 10912776Snikos.nikoleris@arm.com IntReg intRegs[NumIntRegs]; 11012776Snikos.nikoleris@arm.com for (int i = 0; i < NumIntRegs; ++i) 1115609SN/A intRegs[i] = tc.readIntRegFlat(i); 11212776Snikos.nikoleris@arm.com SERIALIZE_ARRAY(intRegs, NumIntRegs); 1135609SN/A 1145609SN/A tc.pcState().serialize(os); 1159409Sandreas.hansson@arm.com 1169235Sandreas.hansson@arm.com // thread_num and cpu_id are deterministic from the config 1173804SN/A} 11812776Snikos.nikoleris@arm.com 1193804SN/Avoid 1203804SN/Aunserialize(ThreadContext &tc, Checkpoint *cp, const std::string §ion) 1218902SN/A{ 1223804SN/A using namespace TheISA; 1233804SN/A 1245608SN/A FloatRegBits floatRegs[NumFloatRegs]; 1255608SN/A // This is a bit ugly, but needed to maintain backwards 1263804SN/A // compatibility. 12712777Sgabeblack@google.com arrayParamIn(cp, section, "floatRegs.i", floatRegs, NumFloatRegs); 1283804SN/A for (int i = 0; i < NumFloatRegs; ++i) 1293804SN/A tc.setFloatRegBitsFlat(i, floatRegs[i]); 1303804SN/A 1315608SN/A IntReg intRegs[NumIntRegs]; 1325608SN/A UNSERIALIZE_ARRAY(intRegs, NumIntRegs); 1333804SN/A for (int i = 0; i < NumIntRegs; ++i) 13412777Sgabeblack@google.com tc.setIntRegFlat(i, intRegs[i]); 13512777Sgabeblack@google.com 13612777Sgabeblack@google.com PCState pcState; 1373804SN/A pcState.unserialize(cp, section); 1383804SN/A tc.pcState(pcState); 1393804SN/A 1405608SN/A // thread_num and cpu_id are deterministic from the config 1415608SN/A} 1423804SN/A 14312777Sgabeblack@google.comvoid 1443804SN/AtakeOverFrom(ThreadContext &ntc, ThreadContext &otc) 1453804SN/A{ 1463804SN/A assert(ntc.getProcessPtr() == otc.getProcessPtr()); 1478918SN/A 1488918SN/A ntc.setStatus(otc.status()); 1498918SN/A ntc.copyArchRegs(&otc); 1508918SN/A ntc.setContextId(otc.contextId()); 1518918SN/A ntc.setThreadId(otc.threadId()); 1528918SN/A 1535608SN/A if (FullSystem) { 1545608SN/A assert(ntc.getSystemPtr() == otc.getSystemPtr()); 1553804SN/A 1563804SN/A BaseCPU *ncpu(ntc.getCpuPtr()); 1573804SN/A assert(ncpu); 1583804SN/A EndQuiesceEvent *oqe(otc.getQuiesceEvent()); 1598918SN/A assert(oqe); 1608918SN/A assert(oqe->tc == &otc); 1618918SN/A 1628918SN/A BaseCPU *ocpu(otc.getCpuPtr()); 1638918SN/A assert(ocpu); 1648918SN/A EndQuiesceEvent *nqe(ntc.getQuiesceEvent()); 1655608SN/A assert(nqe); 1665608SN/A assert(nqe->tc == &ntc); 1673804SN/A 1683804SN/A if (oqe->scheduled()) { 1693804SN/A ncpu->schedule(nqe, oqe->when()); 1703804SN/A ocpu->deschedule(oqe); 1719235Sandreas.hansson@arm.com } 1728918SN/A } 1733804SN/A 1743804SN/A otc.setStatus(ThreadContext::Halted); 1753804SN/A} 1763804SN/A