thread_context.cc revision 11793
1/* 2 * Copyright (c) 2012 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Kevin Lim 42 */ 43 44#include "cpu/thread_context.hh" 45 46#include "arch/kernel_stats.hh" 47#include "base/misc.hh" 48#include "base/trace.hh" 49#include "config/the_isa.hh" 50#include "cpu/base.hh" 51#include "cpu/quiesce_event.hh" 52#include "debug/Context.hh" 53#include "debug/Quiesce.hh" 54#include "params/BaseCPU.hh" 55#include "sim/full_system.hh" 56 57void 58ThreadContext::compare(ThreadContext *one, ThreadContext *two) 59{ 60 DPRINTF(Context, "Comparing thread contexts\n"); 61 62 // First loop through the integer registers. 63 for (int i = 0; i < TheISA::NumIntRegs; ++i) { 64 TheISA::IntReg t1 = one->readIntReg(i); 65 TheISA::IntReg t2 = two->readIntReg(i); 66 if (t1 != t2) 67 panic("Int reg idx %d doesn't match, one: %#x, two: %#x", 68 i, t1, t2); 69 } 70 71 // Then loop through the floating point registers. 72 for (int i = 0; i < TheISA::NumFloatRegs; ++i) { 73 TheISA::FloatRegBits t1 = one->readFloatRegBits(i); 74 TheISA::FloatRegBits t2 = two->readFloatRegBits(i); 75 if (t1 != t2) 76 panic("Float reg idx %d doesn't match, one: %#x, two: %#x", 77 i, t1, t2); 78 } 79 for (int i = 0; i < TheISA::NumMiscRegs; ++i) { 80 TheISA::MiscReg t1 = one->readMiscRegNoEffect(i); 81 TheISA::MiscReg t2 = two->readMiscRegNoEffect(i); 82 if (t1 != t2) 83 panic("Misc reg idx %d doesn't match, one: %#x, two: %#x", 84 i, t1, t2); 85 } 86 87 // loop through the Condition Code registers. 88 for (int i = 0; i < TheISA::NumCCRegs; ++i) { 89 TheISA::CCReg t1 = one->readCCReg(i); 90 TheISA::CCReg t2 = two->readCCReg(i); 91 if (t1 != t2) 92 panic("CC reg idx %d doesn't match, one: %#x, two: %#x", 93 i, t1, t2); 94 } 95 if (!(one->pcState() == two->pcState())) 96 panic("PC state doesn't match."); 97 int id1 = one->cpuId(); 98 int id2 = two->cpuId(); 99 if (id1 != id2) 100 panic("CPU ids don't match, one: %d, two: %d", id1, id2); 101 102 const ContextID cid1 = one->contextId(); 103 const ContextID cid2 = two->contextId(); 104 if (cid1 != cid2) 105 panic("Context ids don't match, one: %d, two: %d", id1, id2); 106 107 108} 109 110void 111ThreadContext::quiesce() 112{ 113 if (!getCpuPtr()->params()->do_quiesce) 114 return; 115 116 DPRINTF(Quiesce, "%s: quiesce()\n", getCpuPtr()->name()); 117 118 suspend(); 119 if (getKernelStats()) 120 getKernelStats()->quiesce(); 121} 122 123 124void 125ThreadContext::quiesceTick(Tick resume) 126{ 127 BaseCPU *cpu = getCpuPtr(); 128 129 if (!cpu->params()->do_quiesce) 130 return; 131 132 EndQuiesceEvent *quiesceEvent = getQuiesceEvent(); 133 134 cpu->reschedule(quiesceEvent, resume, true); 135 136 DPRINTF(Quiesce, "%s: quiesceTick until %lu\n", cpu->name(), resume); 137 138 suspend(); 139 if (getKernelStats()) 140 getKernelStats()->quiesce(); 141} 142 143void 144serialize(ThreadContext &tc, CheckpointOut &cp) 145{ 146 using namespace TheISA; 147 148 FloatRegBits floatRegs[NumFloatRegs]; 149 for (int i = 0; i < NumFloatRegs; ++i) 150 floatRegs[i] = tc.readFloatRegBitsFlat(i); 151 // This is a bit ugly, but needed to maintain backwards 152 // compatibility. 153 arrayParamOut(cp, "floatRegs.i", floatRegs, NumFloatRegs); 154 155 IntReg intRegs[NumIntRegs]; 156 for (int i = 0; i < NumIntRegs; ++i) 157 intRegs[i] = tc.readIntRegFlat(i); 158 SERIALIZE_ARRAY(intRegs, NumIntRegs); 159 160#ifdef ISA_HAS_CC_REGS 161 CCReg ccRegs[NumCCRegs]; 162 for (int i = 0; i < NumCCRegs; ++i) 163 ccRegs[i] = tc.readCCRegFlat(i); 164 SERIALIZE_ARRAY(ccRegs, NumCCRegs); 165#endif 166 167 tc.pcState().serialize(cp); 168 169 // thread_num and cpu_id are deterministic from the config 170} 171 172void 173unserialize(ThreadContext &tc, CheckpointIn &cp) 174{ 175 using namespace TheISA; 176 177 FloatRegBits floatRegs[NumFloatRegs]; 178 // This is a bit ugly, but needed to maintain backwards 179 // compatibility. 180 arrayParamIn(cp, "floatRegs.i", floatRegs, NumFloatRegs); 181 for (int i = 0; i < NumFloatRegs; ++i) 182 tc.setFloatRegBitsFlat(i, floatRegs[i]); 183 184 IntReg intRegs[NumIntRegs]; 185 UNSERIALIZE_ARRAY(intRegs, NumIntRegs); 186 for (int i = 0; i < NumIntRegs; ++i) 187 tc.setIntRegFlat(i, intRegs[i]); 188 189#ifdef ISA_HAS_CC_REGS 190 CCReg ccRegs[NumCCRegs]; 191 UNSERIALIZE_ARRAY(ccRegs, NumCCRegs); 192 for (int i = 0; i < NumCCRegs; ++i) 193 tc.setCCRegFlat(i, ccRegs[i]); 194#endif 195 196 PCState pcState; 197 pcState.unserialize(cp); 198 tc.pcState(pcState); 199 200 // thread_num and cpu_id are deterministic from the config 201} 202 203void 204takeOverFrom(ThreadContext &ntc, ThreadContext &otc) 205{ 206 assert(ntc.getProcessPtr() == otc.getProcessPtr()); 207 208 ntc.setStatus(otc.status()); 209 ntc.copyArchRegs(&otc); 210 ntc.setContextId(otc.contextId()); 211 ntc.setThreadId(otc.threadId()); 212 213 if (FullSystem) { 214 assert(ntc.getSystemPtr() == otc.getSystemPtr()); 215 216 BaseCPU *ncpu(ntc.getCpuPtr()); 217 assert(ncpu); 218 EndQuiesceEvent *oqe(otc.getQuiesceEvent()); 219 assert(oqe); 220 assert(oqe->tc == &otc); 221 222 BaseCPU *ocpu(otc.getCpuPtr()); 223 assert(ocpu); 224 EndQuiesceEvent *nqe(ntc.getQuiesceEvent()); 225 assert(nqe); 226 assert(nqe->tc == &ntc); 227 228 if (oqe->scheduled()) { 229 ncpu->schedule(nqe, oqe->when()); 230 ocpu->deschedule(oqe); 231 } 232 } 233 234 otc.setStatus(ThreadContext::Halted); 235} 236