thread_context.cc revision 11005
15217Ssaidi@eecs.umich.edu/* 29428SAndreas.Sandberg@ARM.com * Copyright (c) 2012 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 49428SAndreas.Sandberg@ARM.com * All rights reserved 59428SAndreas.Sandberg@ARM.com * 69428SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall 79428SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual 89428SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating 99428SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software 109428SAndreas.Sandberg@ARM.com * licensed hereunder. You may use the software subject to the license 119428SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated 129428SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software, 139428SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form. 149428SAndreas.Sandberg@ARM.com * 155217Ssaidi@eecs.umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 165217Ssaidi@eecs.umich.edu * All rights reserved. 175217Ssaidi@eecs.umich.edu * 185217Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 195217Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 205217Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 215217Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 225217Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 235217Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 245217Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 255217Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its 265217Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 275217Ssaidi@eecs.umich.edu * this software without specific prior written permission. 285217Ssaidi@eecs.umich.edu * 295217Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 305217Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 315217Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 325217Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 335217Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 345217Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 355217Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 365217Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 375217Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 385217Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 395217Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 405217Ssaidi@eecs.umich.edu * 415217Ssaidi@eecs.umich.edu * Authors: Kevin Lim 425217Ssaidi@eecs.umich.edu */ 435217Ssaidi@eecs.umich.edu 445217Ssaidi@eecs.umich.edu#include "base/misc.hh" 455217Ssaidi@eecs.umich.edu#include "base/trace.hh" 466658Snate@binkert.org#include "config/the_isa.hh" 479441SAndreas.Sandberg@ARM.com#include "cpu/base.hh" 489441SAndreas.Sandberg@ARM.com#include "cpu/quiesce_event.hh" 495217Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 508232Snate@binkert.org#include "debug/Context.hh" 519441SAndreas.Sandberg@ARM.com#include "sim/full_system.hh" 525217Ssaidi@eecs.umich.edu 535217Ssaidi@eecs.umich.eduvoid 545217Ssaidi@eecs.umich.eduThreadContext::compare(ThreadContext *one, ThreadContext *two) 555217Ssaidi@eecs.umich.edu{ 565217Ssaidi@eecs.umich.edu DPRINTF(Context, "Comparing thread contexts\n"); 575217Ssaidi@eecs.umich.edu 585217Ssaidi@eecs.umich.edu // First loop through the integer registers. 595217Ssaidi@eecs.umich.edu for (int i = 0; i < TheISA::NumIntRegs; ++i) { 605217Ssaidi@eecs.umich.edu TheISA::IntReg t1 = one->readIntReg(i); 615217Ssaidi@eecs.umich.edu TheISA::IntReg t2 = two->readIntReg(i); 625217Ssaidi@eecs.umich.edu if (t1 != t2) 635217Ssaidi@eecs.umich.edu panic("Int reg idx %d doesn't match, one: %#x, two: %#x", 645217Ssaidi@eecs.umich.edu i, t1, t2); 655217Ssaidi@eecs.umich.edu } 665217Ssaidi@eecs.umich.edu 675217Ssaidi@eecs.umich.edu // Then loop through the floating point registers. 685217Ssaidi@eecs.umich.edu for (int i = 0; i < TheISA::NumFloatRegs; ++i) { 695217Ssaidi@eecs.umich.edu TheISA::FloatRegBits t1 = one->readFloatRegBits(i); 705217Ssaidi@eecs.umich.edu TheISA::FloatRegBits t2 = two->readFloatRegBits(i); 715217Ssaidi@eecs.umich.edu if (t1 != t2) 725217Ssaidi@eecs.umich.edu panic("Float reg idx %d doesn't match, one: %#x, two: %#x", 735217Ssaidi@eecs.umich.edu i, t1, t2); 745217Ssaidi@eecs.umich.edu } 755217Ssaidi@eecs.umich.edu for (int i = 0; i < TheISA::NumMiscRegs; ++i) { 765217Ssaidi@eecs.umich.edu TheISA::MiscReg t1 = one->readMiscRegNoEffect(i); 775217Ssaidi@eecs.umich.edu TheISA::MiscReg t2 = two->readMiscRegNoEffect(i); 785217Ssaidi@eecs.umich.edu if (t1 != t2) 795217Ssaidi@eecs.umich.edu panic("Misc reg idx %d doesn't match, one: %#x, two: %#x", 805217Ssaidi@eecs.umich.edu i, t1, t2); 815217Ssaidi@eecs.umich.edu } 825217Ssaidi@eecs.umich.edu 839920Syasuko.eckert@amd.com // loop through the Condition Code registers. 849920Syasuko.eckert@amd.com for (int i = 0; i < TheISA::NumCCRegs; ++i) { 859920Syasuko.eckert@amd.com TheISA::CCReg t1 = one->readCCReg(i); 869920Syasuko.eckert@amd.com TheISA::CCReg t2 = two->readCCReg(i); 879920Syasuko.eckert@amd.com if (t1 != t2) 889920Syasuko.eckert@amd.com panic("CC reg idx %d doesn't match, one: %#x, two: %#x", 899920Syasuko.eckert@amd.com i, t1, t2); 909920Syasuko.eckert@amd.com } 917720Sgblack@eecs.umich.edu if (!(one->pcState() == two->pcState())) 927720Sgblack@eecs.umich.edu panic("PC state doesn't match."); 935712Shsul@eecs.umich.edu int id1 = one->cpuId(); 945712Shsul@eecs.umich.edu int id2 = two->cpuId(); 955217Ssaidi@eecs.umich.edu if (id1 != id2) 965217Ssaidi@eecs.umich.edu panic("CPU ids don't match, one: %d, two: %d", id1, id2); 975714Shsul@eecs.umich.edu 9811005Sandreas.sandberg@arm.com const ContextID cid1 = one->contextId(); 9911005Sandreas.sandberg@arm.com const ContextID cid2 = two->contextId(); 10011005Sandreas.sandberg@arm.com if (cid1 != cid2) 1015714Shsul@eecs.umich.edu panic("Context ids don't match, one: %d, two: %d", id1, id2); 1025714Shsul@eecs.umich.edu 1035714Shsul@eecs.umich.edu 1045217Ssaidi@eecs.umich.edu} 1059428SAndreas.Sandberg@ARM.com 1069428SAndreas.Sandberg@ARM.comvoid 10710905Sandreas.sandberg@arm.comserialize(ThreadContext &tc, CheckpointOut &cp) 1089428SAndreas.Sandberg@ARM.com{ 1099428SAndreas.Sandberg@ARM.com using namespace TheISA; 1109428SAndreas.Sandberg@ARM.com 1119428SAndreas.Sandberg@ARM.com FloatRegBits floatRegs[NumFloatRegs]; 1129428SAndreas.Sandberg@ARM.com for (int i = 0; i < NumFloatRegs; ++i) 1139428SAndreas.Sandberg@ARM.com floatRegs[i] = tc.readFloatRegBitsFlat(i); 1149428SAndreas.Sandberg@ARM.com // This is a bit ugly, but needed to maintain backwards 1159428SAndreas.Sandberg@ARM.com // compatibility. 11610905Sandreas.sandberg@arm.com arrayParamOut(cp, "floatRegs.i", floatRegs, NumFloatRegs); 1179428SAndreas.Sandberg@ARM.com 1189428SAndreas.Sandberg@ARM.com IntReg intRegs[NumIntRegs]; 1199428SAndreas.Sandberg@ARM.com for (int i = 0; i < NumIntRegs; ++i) 1209428SAndreas.Sandberg@ARM.com intRegs[i] = tc.readIntRegFlat(i); 1219428SAndreas.Sandberg@ARM.com SERIALIZE_ARRAY(intRegs, NumIntRegs); 1229428SAndreas.Sandberg@ARM.com 1239920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 1249920Syasuko.eckert@amd.com CCReg ccRegs[NumCCRegs]; 1259920Syasuko.eckert@amd.com for (int i = 0; i < NumCCRegs; ++i) 1269920Syasuko.eckert@amd.com ccRegs[i] = tc.readCCRegFlat(i); 1279920Syasuko.eckert@amd.com SERIALIZE_ARRAY(ccRegs, NumCCRegs); 1289920Syasuko.eckert@amd.com#endif 1299920Syasuko.eckert@amd.com 13010905Sandreas.sandberg@arm.com tc.pcState().serialize(cp); 1319428SAndreas.Sandberg@ARM.com 1329428SAndreas.Sandberg@ARM.com // thread_num and cpu_id are deterministic from the config 1339428SAndreas.Sandberg@ARM.com} 1349428SAndreas.Sandberg@ARM.com 1359428SAndreas.Sandberg@ARM.comvoid 13610905Sandreas.sandberg@arm.comunserialize(ThreadContext &tc, CheckpointIn &cp) 1379428SAndreas.Sandberg@ARM.com{ 1389428SAndreas.Sandberg@ARM.com using namespace TheISA; 1399428SAndreas.Sandberg@ARM.com 1409428SAndreas.Sandberg@ARM.com FloatRegBits floatRegs[NumFloatRegs]; 1419428SAndreas.Sandberg@ARM.com // This is a bit ugly, but needed to maintain backwards 1429428SAndreas.Sandberg@ARM.com // compatibility. 14310905Sandreas.sandberg@arm.com arrayParamIn(cp, "floatRegs.i", floatRegs, NumFloatRegs); 1449428SAndreas.Sandberg@ARM.com for (int i = 0; i < NumFloatRegs; ++i) 1459428SAndreas.Sandberg@ARM.com tc.setFloatRegBitsFlat(i, floatRegs[i]); 1469428SAndreas.Sandberg@ARM.com 1479428SAndreas.Sandberg@ARM.com IntReg intRegs[NumIntRegs]; 1489428SAndreas.Sandberg@ARM.com UNSERIALIZE_ARRAY(intRegs, NumIntRegs); 1499428SAndreas.Sandberg@ARM.com for (int i = 0; i < NumIntRegs; ++i) 1509428SAndreas.Sandberg@ARM.com tc.setIntRegFlat(i, intRegs[i]); 1519428SAndreas.Sandberg@ARM.com 1529920Syasuko.eckert@amd.com#ifdef ISA_HAS_CC_REGS 1539920Syasuko.eckert@amd.com CCReg ccRegs[NumCCRegs]; 1549920Syasuko.eckert@amd.com UNSERIALIZE_ARRAY(ccRegs, NumCCRegs); 1559920Syasuko.eckert@amd.com for (int i = 0; i < NumCCRegs; ++i) 1569920Syasuko.eckert@amd.com tc.setCCRegFlat(i, ccRegs[i]); 1579920Syasuko.eckert@amd.com#endif 1589920Syasuko.eckert@amd.com 1599428SAndreas.Sandberg@ARM.com PCState pcState; 16010905Sandreas.sandberg@arm.com pcState.unserialize(cp); 1619428SAndreas.Sandberg@ARM.com tc.pcState(pcState); 1629428SAndreas.Sandberg@ARM.com 1639428SAndreas.Sandberg@ARM.com // thread_num and cpu_id are deterministic from the config 1649428SAndreas.Sandberg@ARM.com} 1659441SAndreas.Sandberg@ARM.com 1669441SAndreas.Sandberg@ARM.comvoid 1679441SAndreas.Sandberg@ARM.comtakeOverFrom(ThreadContext &ntc, ThreadContext &otc) 1689441SAndreas.Sandberg@ARM.com{ 1699441SAndreas.Sandberg@ARM.com assert(ntc.getProcessPtr() == otc.getProcessPtr()); 1709441SAndreas.Sandberg@ARM.com 1719441SAndreas.Sandberg@ARM.com ntc.setStatus(otc.status()); 1729441SAndreas.Sandberg@ARM.com ntc.copyArchRegs(&otc); 1739441SAndreas.Sandberg@ARM.com ntc.setContextId(otc.contextId()); 1749441SAndreas.Sandberg@ARM.com ntc.setThreadId(otc.threadId()); 1759441SAndreas.Sandberg@ARM.com 1769441SAndreas.Sandberg@ARM.com if (FullSystem) { 1779441SAndreas.Sandberg@ARM.com assert(ntc.getSystemPtr() == otc.getSystemPtr()); 1789441SAndreas.Sandberg@ARM.com 1799441SAndreas.Sandberg@ARM.com BaseCPU *ncpu(ntc.getCpuPtr()); 1809441SAndreas.Sandberg@ARM.com assert(ncpu); 1819441SAndreas.Sandberg@ARM.com EndQuiesceEvent *oqe(otc.getQuiesceEvent()); 1829441SAndreas.Sandberg@ARM.com assert(oqe); 1839441SAndreas.Sandberg@ARM.com assert(oqe->tc == &otc); 1849441SAndreas.Sandberg@ARM.com 1859441SAndreas.Sandberg@ARM.com BaseCPU *ocpu(otc.getCpuPtr()); 1869441SAndreas.Sandberg@ARM.com assert(ocpu); 1879441SAndreas.Sandberg@ARM.com EndQuiesceEvent *nqe(ntc.getQuiesceEvent()); 1889441SAndreas.Sandberg@ARM.com assert(nqe); 1899441SAndreas.Sandberg@ARM.com assert(nqe->tc == &ntc); 1909441SAndreas.Sandberg@ARM.com 1919441SAndreas.Sandberg@ARM.com if (oqe->scheduled()) { 1929441SAndreas.Sandberg@ARM.com ncpu->schedule(nqe, oqe->when()); 1939441SAndreas.Sandberg@ARM.com ocpu->deschedule(oqe); 1949441SAndreas.Sandberg@ARM.com } 1959441SAndreas.Sandberg@ARM.com } 1969441SAndreas.Sandberg@ARM.com 1979441SAndreas.Sandberg@ARM.com otc.setStatus(ThreadContext::Halted); 1989441SAndreas.Sandberg@ARM.com} 199