thread_context.cc revision 10905
112740Sandreas.sandberg@arm.com/* 212740Sandreas.sandberg@arm.com * Copyright (c) 2012 ARM Limited 312740Sandreas.sandberg@arm.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 412740Sandreas.sandberg@arm.com * All rights reserved 512740Sandreas.sandberg@arm.com * 612740Sandreas.sandberg@arm.com * The license below extends only to copyright in the software and shall 712740Sandreas.sandberg@arm.com * not be construed as granting a license to any other intellectual 812740Sandreas.sandberg@arm.com * property including but not limited to intellectual property relating 912740Sandreas.sandberg@arm.com * to a hardware implementation of the functionality of the software 1012740Sandreas.sandberg@arm.com * licensed hereunder. You may use the software subject to the license 1112740Sandreas.sandberg@arm.com * terms below provided that you ensure that this notice is replicated 1212740Sandreas.sandberg@arm.com * unmodified and in its entirety in all distributions of the software, 1312740Sandreas.sandberg@arm.com * modified or unmodified, in source code or in binary form. 1412740Sandreas.sandberg@arm.com * 1512740Sandreas.sandberg@arm.com * Copyright (c) 2006 The Regents of The University of Michigan 1612740Sandreas.sandberg@arm.com * All rights reserved. 1712740Sandreas.sandberg@arm.com * 1812740Sandreas.sandberg@arm.com * Redistribution and use in source and binary forms, with or without 1912740Sandreas.sandberg@arm.com * modification, are permitted provided that the following conditions are 2012740Sandreas.sandberg@arm.com * met: redistributions of source code must retain the above copyright 2112740Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer; 2212740Sandreas.sandberg@arm.com * redistributions in binary form must reproduce the above copyright 2312740Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer in the 2412740Sandreas.sandberg@arm.com * documentation and/or other materials provided with the distribution; 2512740Sandreas.sandberg@arm.com * neither the name of the copyright holders nor the names of its 2612740Sandreas.sandberg@arm.com * contributors may be used to endorse or promote products derived from 2712740Sandreas.sandberg@arm.com * this software without specific prior written permission. 2812740Sandreas.sandberg@arm.com * 2912740Sandreas.sandberg@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3012740Sandreas.sandberg@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3112740Sandreas.sandberg@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3212740Sandreas.sandberg@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3312740Sandreas.sandberg@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3412740Sandreas.sandberg@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3512740Sandreas.sandberg@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3612740Sandreas.sandberg@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3712740Sandreas.sandberg@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3812740Sandreas.sandberg@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3912740Sandreas.sandberg@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4012740Sandreas.sandberg@arm.com * 4112740Sandreas.sandberg@arm.com * Authors: Kevin Lim 4212740Sandreas.sandberg@arm.com */ 4312740Sandreas.sandberg@arm.com 4412740Sandreas.sandberg@arm.com#include "base/misc.hh" 4512740Sandreas.sandberg@arm.com#include "base/trace.hh" 4612740Sandreas.sandberg@arm.com#include "config/the_isa.hh" 4712740Sandreas.sandberg@arm.com#include "cpu/base.hh" 4812740Sandreas.sandberg@arm.com#include "cpu/quiesce_event.hh" 4912740Sandreas.sandberg@arm.com#include "cpu/thread_context.hh" 5012740Sandreas.sandberg@arm.com#include "debug/Context.hh" 5112740Sandreas.sandberg@arm.com#include "sim/full_system.hh" 5212740Sandreas.sandberg@arm.com 5312740Sandreas.sandberg@arm.comvoid 5412740Sandreas.sandberg@arm.comThreadContext::compare(ThreadContext *one, ThreadContext *two) 5512740Sandreas.sandberg@arm.com{ 5612740Sandreas.sandberg@arm.com DPRINTF(Context, "Comparing thread contexts\n"); 5712740Sandreas.sandberg@arm.com 5812740Sandreas.sandberg@arm.com // First loop through the integer registers. 5912740Sandreas.sandberg@arm.com for (int i = 0; i < TheISA::NumIntRegs; ++i) { 6012740Sandreas.sandberg@arm.com TheISA::IntReg t1 = one->readIntReg(i); 6112740Sandreas.sandberg@arm.com TheISA::IntReg t2 = two->readIntReg(i); 6212740Sandreas.sandberg@arm.com if (t1 != t2) 6312740Sandreas.sandberg@arm.com panic("Int reg idx %d doesn't match, one: %#x, two: %#x", 6412740Sandreas.sandberg@arm.com i, t1, t2); 6512740Sandreas.sandberg@arm.com } 6612740Sandreas.sandberg@arm.com 6712740Sandreas.sandberg@arm.com // Then loop through the floating point registers. 6812740Sandreas.sandberg@arm.com for (int i = 0; i < TheISA::NumFloatRegs; ++i) { 6912740Sandreas.sandberg@arm.com TheISA::FloatRegBits t1 = one->readFloatRegBits(i); 7012740Sandreas.sandberg@arm.com TheISA::FloatRegBits t2 = two->readFloatRegBits(i); 7112740Sandreas.sandberg@arm.com if (t1 != t2) 7212740Sandreas.sandberg@arm.com panic("Float reg idx %d doesn't match, one: %#x, two: %#x", 7312740Sandreas.sandberg@arm.com i, t1, t2); 7412740Sandreas.sandberg@arm.com } 7512740Sandreas.sandberg@arm.com for (int i = 0; i < TheISA::NumMiscRegs; ++i) { 7612740Sandreas.sandberg@arm.com TheISA::MiscReg t1 = one->readMiscRegNoEffect(i); 7712740Sandreas.sandberg@arm.com TheISA::MiscReg t2 = two->readMiscRegNoEffect(i); 7812740Sandreas.sandberg@arm.com if (t1 != t2) 7912740Sandreas.sandberg@arm.com panic("Misc reg idx %d doesn't match, one: %#x, two: %#x", 8012740Sandreas.sandberg@arm.com i, t1, t2); 8112740Sandreas.sandberg@arm.com } 8212740Sandreas.sandberg@arm.com 8312740Sandreas.sandberg@arm.com // loop through the Condition Code registers. 8412740Sandreas.sandberg@arm.com for (int i = 0; i < TheISA::NumCCRegs; ++i) { 8512740Sandreas.sandberg@arm.com TheISA::CCReg t1 = one->readCCReg(i); 8612740Sandreas.sandberg@arm.com TheISA::CCReg t2 = two->readCCReg(i); 8712740Sandreas.sandberg@arm.com if (t1 != t2) 8812740Sandreas.sandberg@arm.com panic("CC reg idx %d doesn't match, one: %#x, two: %#x", 8912740Sandreas.sandberg@arm.com i, t1, t2); 9012740Sandreas.sandberg@arm.com } 9112740Sandreas.sandberg@arm.com if (!(one->pcState() == two->pcState())) 9212740Sandreas.sandberg@arm.com panic("PC state doesn't match."); 9312740Sandreas.sandberg@arm.com int id1 = one->cpuId(); 9412740Sandreas.sandberg@arm.com int id2 = two->cpuId(); 9512740Sandreas.sandberg@arm.com if (id1 != id2) 9612740Sandreas.sandberg@arm.com panic("CPU ids don't match, one: %d, two: %d", id1, id2); 9712740Sandreas.sandberg@arm.com 9812740Sandreas.sandberg@arm.com id1 = one->contextId(); 9912740Sandreas.sandberg@arm.com id2 = two->contextId(); 10012740Sandreas.sandberg@arm.com if (id1 != id2) 10112740Sandreas.sandberg@arm.com panic("Context ids don't match, one: %d, two: %d", id1, id2); 10212740Sandreas.sandberg@arm.com 10312740Sandreas.sandberg@arm.com 10412740Sandreas.sandberg@arm.com} 10512740Sandreas.sandberg@arm.com 10612740Sandreas.sandberg@arm.comvoid 10712740Sandreas.sandberg@arm.comserialize(ThreadContext &tc, CheckpointOut &cp) 10812740Sandreas.sandberg@arm.com{ 10912740Sandreas.sandberg@arm.com using namespace TheISA; 11012740Sandreas.sandberg@arm.com 11112740Sandreas.sandberg@arm.com FloatRegBits floatRegs[NumFloatRegs]; 11212740Sandreas.sandberg@arm.com for (int i = 0; i < NumFloatRegs; ++i) 11312740Sandreas.sandberg@arm.com floatRegs[i] = tc.readFloatRegBitsFlat(i); 11412740Sandreas.sandberg@arm.com // This is a bit ugly, but needed to maintain backwards 11512740Sandreas.sandberg@arm.com // compatibility. 11612740Sandreas.sandberg@arm.com arrayParamOut(cp, "floatRegs.i", floatRegs, NumFloatRegs); 11712740Sandreas.sandberg@arm.com 11812740Sandreas.sandberg@arm.com IntReg intRegs[NumIntRegs]; 11912740Sandreas.sandberg@arm.com for (int i = 0; i < NumIntRegs; ++i) 12012740Sandreas.sandberg@arm.com intRegs[i] = tc.readIntRegFlat(i); 12112740Sandreas.sandberg@arm.com SERIALIZE_ARRAY(intRegs, NumIntRegs); 12212740Sandreas.sandberg@arm.com 12312740Sandreas.sandberg@arm.com#ifdef ISA_HAS_CC_REGS 12412740Sandreas.sandberg@arm.com CCReg ccRegs[NumCCRegs]; 12512740Sandreas.sandberg@arm.com for (int i = 0; i < NumCCRegs; ++i) 12612740Sandreas.sandberg@arm.com ccRegs[i] = tc.readCCRegFlat(i); 12712740Sandreas.sandberg@arm.com SERIALIZE_ARRAY(ccRegs, NumCCRegs); 12812740Sandreas.sandberg@arm.com#endif 12912740Sandreas.sandberg@arm.com 13012740Sandreas.sandberg@arm.com tc.pcState().serialize(cp); 13112740Sandreas.sandberg@arm.com 13212740Sandreas.sandberg@arm.com // thread_num and cpu_id are deterministic from the config 13312740Sandreas.sandberg@arm.com} 13412740Sandreas.sandberg@arm.com 13512740Sandreas.sandberg@arm.comvoid 13612740Sandreas.sandberg@arm.comunserialize(ThreadContext &tc, CheckpointIn &cp) 13712740Sandreas.sandberg@arm.com{ 13812740Sandreas.sandberg@arm.com using namespace TheISA; 13912740Sandreas.sandberg@arm.com 14012740Sandreas.sandberg@arm.com FloatRegBits floatRegs[NumFloatRegs]; 14112740Sandreas.sandberg@arm.com // This is a bit ugly, but needed to maintain backwards 14212740Sandreas.sandberg@arm.com // compatibility. 14312740Sandreas.sandberg@arm.com arrayParamIn(cp, "floatRegs.i", floatRegs, NumFloatRegs); 14412740Sandreas.sandberg@arm.com for (int i = 0; i < NumFloatRegs; ++i) 14512740Sandreas.sandberg@arm.com tc.setFloatRegBitsFlat(i, floatRegs[i]); 14612740Sandreas.sandberg@arm.com 14712740Sandreas.sandberg@arm.com IntReg intRegs[NumIntRegs]; 14812740Sandreas.sandberg@arm.com UNSERIALIZE_ARRAY(intRegs, NumIntRegs); 14912740Sandreas.sandberg@arm.com for (int i = 0; i < NumIntRegs; ++i) 15012740Sandreas.sandberg@arm.com tc.setIntRegFlat(i, intRegs[i]); 15112740Sandreas.sandberg@arm.com 15212740Sandreas.sandberg@arm.com#ifdef ISA_HAS_CC_REGS 15312740Sandreas.sandberg@arm.com CCReg ccRegs[NumCCRegs]; 15412740Sandreas.sandberg@arm.com UNSERIALIZE_ARRAY(ccRegs, NumCCRegs); 15512740Sandreas.sandberg@arm.com for (int i = 0; i < NumCCRegs; ++i) 15612740Sandreas.sandberg@arm.com tc.setCCRegFlat(i, ccRegs[i]); 15712740Sandreas.sandberg@arm.com#endif 15812740Sandreas.sandberg@arm.com 15912740Sandreas.sandberg@arm.com PCState pcState; 16012740Sandreas.sandberg@arm.com pcState.unserialize(cp); 16112740Sandreas.sandberg@arm.com tc.pcState(pcState); 16212740Sandreas.sandberg@arm.com 16312740Sandreas.sandberg@arm.com // thread_num and cpu_id are deterministic from the config 16412740Sandreas.sandberg@arm.com} 16512740Sandreas.sandberg@arm.com 16612740Sandreas.sandberg@arm.comvoid 16712740Sandreas.sandberg@arm.comtakeOverFrom(ThreadContext &ntc, ThreadContext &otc) 16812740Sandreas.sandberg@arm.com{ 16912740Sandreas.sandberg@arm.com assert(ntc.getProcessPtr() == otc.getProcessPtr()); 17012740Sandreas.sandberg@arm.com 17112740Sandreas.sandberg@arm.com ntc.setStatus(otc.status()); 17212740Sandreas.sandberg@arm.com ntc.copyArchRegs(&otc); 17312740Sandreas.sandberg@arm.com ntc.setContextId(otc.contextId()); 17412740Sandreas.sandberg@arm.com ntc.setThreadId(otc.threadId()); 17512740Sandreas.sandberg@arm.com 17612740Sandreas.sandberg@arm.com if (FullSystem) { 17712740Sandreas.sandberg@arm.com assert(ntc.getSystemPtr() == otc.getSystemPtr()); 17812740Sandreas.sandberg@arm.com 17912740Sandreas.sandberg@arm.com BaseCPU *ncpu(ntc.getCpuPtr()); 18012740Sandreas.sandberg@arm.com assert(ncpu); 18112740Sandreas.sandberg@arm.com EndQuiesceEvent *oqe(otc.getQuiesceEvent()); 18212740Sandreas.sandberg@arm.com assert(oqe); 18312740Sandreas.sandberg@arm.com assert(oqe->tc == &otc); 18412740Sandreas.sandberg@arm.com 18512740Sandreas.sandberg@arm.com BaseCPU *ocpu(otc.getCpuPtr()); 18612740Sandreas.sandberg@arm.com assert(ocpu); 18712740Sandreas.sandberg@arm.com EndQuiesceEvent *nqe(ntc.getQuiesceEvent()); 18812740Sandreas.sandberg@arm.com assert(nqe); 18912740Sandreas.sandberg@arm.com assert(nqe->tc == &ntc); 19012740Sandreas.sandberg@arm.com 19112740Sandreas.sandberg@arm.com if (oqe->scheduled()) { 19212740Sandreas.sandberg@arm.com ncpu->schedule(nqe, oqe->when()); 19312740Sandreas.sandberg@arm.com ocpu->deschedule(oqe); 19412740Sandreas.sandberg@arm.com } 19512740Sandreas.sandberg@arm.com } 19612740Sandreas.sandberg@arm.com 19712740Sandreas.sandberg@arm.com otc.setStatus(ThreadContext::Halted); 19812740Sandreas.sandberg@arm.com} 19912740Sandreas.sandberg@arm.com