traffic_gen.hh revision 12397:a6d362560825
1/*
2 * Copyright (c) 2012-2013, 2016-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
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15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
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21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Thomas Grass
38 *          Andreas Hansson
39 *          Sascha Bischoff
40 */
41
42#ifndef __CPU_TRAFFIC_GEN_TRAFFIC_GEN_HH__
43#define __CPU_TRAFFIC_GEN_TRAFFIC_GEN_HH__
44
45#include <unordered_map>
46
47#include "base/statistics.hh"
48#include "cpu/testers/traffic_gen/base_gen.hh"
49#include "cpu/testers/traffic_gen/dram_gen.hh"
50#include "cpu/testers/traffic_gen/dram_rot_gen.hh"
51#include "cpu/testers/traffic_gen/exit_gen.hh"
52#include "cpu/testers/traffic_gen/idle_gen.hh"
53#include "cpu/testers/traffic_gen/linear_gen.hh"
54#include "cpu/testers/traffic_gen/random_gen.hh"
55#include "cpu/testers/traffic_gen/trace_gen.hh"
56#include "mem/mem_object.hh"
57#include "mem/qport.hh"
58#include "params/TrafficGen.hh"
59
60/**
61 * The traffic generator is a master module that generates stimuli for
62 * the memory system, based on a collection of simple generator
63 * behaviours that are either probabilistic or based on traces. It can
64 * be used stand alone for creating test cases for interconnect and
65 * memory controllers, or function as a black box replacement for
66 * system components that are not yet modelled in detail, e.g. a video
67 * engine or baseband subsystem.
68 */
69class TrafficGen : public MemObject
70{
71
72  private:
73
74    /**
75     * Determine next state and perform the transition.
76     */
77    void transition();
78
79    /**
80     * Enter a new state.
81     *
82     * @param newState identifier of state to enter
83     */
84    void enterState(uint32_t newState);
85
86    /**
87     * Resolve a file path in the configuration file.
88     *
89     * This method resolves a relative path to a file that has been
90     * referenced in the configuration file. It first tries to resolve
91     * the file relative to the configuration file's path. If that
92     * fails, it falls back to constructing a path relative to the
93     * current working directory.
94     *
95     * Absolute paths are returned unmodified.
96     *
97     * @param name Path to resolve
98     */
99    std::string resolveFile(const std::string &name);
100
101    /**
102     * Parse the config file and build the state map and
103     * transition matrix.
104     */
105    void parseConfig();
106
107    /**
108     * Schedules event for next update and executes an update on the
109     * state graph, either performing a state transition or executing
110     * the current state, depending on the current time.
111     */
112    void update();
113
114    /**
115     * Receive a retry from the neighbouring port and attempt to
116     * resend the waiting packet.
117     */
118    void recvReqRetry();
119
120    /**
121     * Method to inform the user we have made no progress.
122     */
123    void noProgress();
124
125    /** Struct to represent a probabilistic transition during parsing. */
126    struct Transition {
127        uint32_t from;
128        uint32_t to;
129        double p;
130    };
131
132    /**
133     * The system used to determine which mode we are currently operating
134     * in.
135     */
136    System* system;
137
138    /**
139     * MasterID used in generated requests.
140     */
141    MasterID masterID;
142
143    /**
144     * The config file to parse.
145     */
146    const std::string configFile;
147
148    /**
149     * Determine whether to add elasticity in the request injection,
150     * thus responding to backpressure by slowing things down.
151     */
152    const bool elasticReq;
153
154    /**
155     * Time to tolerate waiting for retries (not making progress),
156     * until we declare things broken.
157     */
158    const Tick progressCheck;
159
160    /**
161     * Event to keep track of our progress, or lack thereof.
162     */
163    EventFunctionWrapper noProgressEvent;
164
165    /** Time of next transition */
166    Tick nextTransitionTick;
167
168    /** Time of the next packet. */
169    Tick nextPacketTick;
170
171    /** State transition matrix */
172    std::vector<std::vector<double> > transitionMatrix;
173
174    /** Index of the current state */
175    uint32_t currState;
176
177    /** Map of generator states */
178    std::unordered_map<uint32_t, BaseGen*> states;
179
180    /** Master port specialisation for the traffic generator */
181    class TrafficGenPort : public MasterPort
182    {
183      public:
184
185        TrafficGenPort(const std::string& name, TrafficGen& traffic_gen)
186            : MasterPort(name, &traffic_gen), trafficGen(traffic_gen)
187        { }
188
189      protected:
190
191        void recvReqRetry() { trafficGen.recvReqRetry(); }
192
193        bool recvTimingResp(PacketPtr pkt);
194
195        void recvTimingSnoopReq(PacketPtr pkt) { }
196
197        void recvFunctionalSnoop(PacketPtr pkt) { }
198
199        Tick recvAtomicSnoop(PacketPtr pkt) { return 0; }
200
201      private:
202
203        TrafficGen& trafficGen;
204
205    };
206
207    /** The instance of master port used by the traffic generator. */
208    TrafficGenPort port;
209
210    /** Packet waiting to be sent. */
211    PacketPtr retryPkt;
212
213    /** Tick when the stalled packet was meant to be sent. */
214    Tick retryPktTick;
215
216    /** Event for scheduling updates */
217    EventFunctionWrapper updateEvent;
218
219    uint64_t numSuppressed;
220
221    /** Count the number of generated packets. */
222    Stats::Scalar numPackets;
223
224    /** Count the number of retries. */
225    Stats::Scalar numRetries;
226
227    /** Count the time incurred from back-pressure. */
228    Stats::Scalar retryTicks;
229
230  public:
231
232    TrafficGen(const TrafficGenParams* p);
233
234    ~TrafficGen() {}
235
236    BaseMasterPort& getMasterPort(const std::string &if_name,
237                                  PortID idx = InvalidPortID) override;
238
239    void init() override;
240
241    void initState() override;
242
243    DrainState drain() override;
244
245    void serialize(CheckpointOut &cp) const override;
246    void unserialize(CheckpointIn &cp) override;
247
248    /** Register statistics */
249    void regStats() override;
250
251};
252
253#endif //__CPU_TRAFFIC_GEN_TRAFFIC_GEN_HH__
254