linear_gen.hh revision 12804:f47e75dce5c6
1/* 2 * Copyright (c) 2012-2013, 2017 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed here under. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Thomas Grass 38 * Andreas Hansson 39 * Sascha Bischoff 40 * Neha Agarwal 41 */ 42 43/** 44 * @file 45 * Declaration of the linear generator that generates sequential 46 * requests. 47 */ 48 49#ifndef __CPU_TRAFFIC_GEN_LINEAR_GEN_HH__ 50#define __CPU_TRAFFIC_GEN_LINEAR_GEN_HH__ 51 52#include "base/bitfield.hh" 53#include "base/intmath.hh" 54#include "base_gen.hh" 55#include "mem/packet.hh" 56 57/** 58 * The linear generator generates sequential requests from a 59 * start to an end address, with a fixed block size. A 60 * fraction of the requests are reads, as determined by the 61 * read percent. There is an optional data limit for when to 62 * stop generating new requests. 63 */ 64class LinearGen : public BaseGen 65{ 66 67 public: 68 69 /** 70 * Create a linear address sequence generator. Set 71 * min_period == max_period for a fixed inter-transaction 72 * time. 73 * 74 * @param _name Name to use for status and debug 75 * @param master_id MasterID set on each request 76 * @param _duration duration of this state before transitioning 77 * @param start_addr Start address 78 * @param end_addr End address 79 * @param _blocksize Size used for transactions injected 80 * @param min_period Lower limit of random inter-transaction time 81 * @param max_period Upper limit of random inter-transaction time 82 * @param read_percent Percent of transactions that are reads 83 * @param data_limit Upper limit on how much data to read/write 84 */ 85 LinearGen(const std::string& _name, MasterID master_id, Tick _duration, 86 Addr start_addr, Addr end_addr, Addr _blocksize, 87 Tick min_period, Tick max_period, 88 uint8_t read_percent, Addr data_limit) 89 : BaseGen(_name, master_id, _duration), 90 startAddr(start_addr), endAddr(end_addr), 91 blocksize(_blocksize), minPeriod(min_period), 92 maxPeriod(max_period), readPercent(read_percent), 93 dataLimit(data_limit), nextAddr(startAddr), dataManipulated(0) 94 { } 95 96 void enter(); 97 98 PacketPtr getNextPacket(); 99 100 Tick nextPacketTick(bool elastic, Tick delay) const; 101 102 private: 103 104 /** Start of address range */ 105 const Addr startAddr; 106 107 /** End of address range */ 108 const Addr endAddr; 109 110 /** Blocksize and address increment */ 111 const Addr blocksize; 112 113 /** Request generation period */ 114 const Tick minPeriod; 115 const Tick maxPeriod; 116 117 /** 118 * Percent of generated transactions that should be reads 119 */ 120 const uint8_t readPercent; 121 122 /** Maximum amount of data to manipulate */ 123 const Addr dataLimit; 124 125 /** Address of next request */ 126 Addr nextAddr; 127 128 /** 129 * Counter to determine the amount of data 130 * manipulated. Used to determine if we should continue 131 * generating requests. 132 */ 133 Addr dataManipulated; 134}; 135 136#endif 137