dram_rot_gen.hh revision 12844:c934a1338314 
1/*
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23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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36 *
37 * Authors: Thomas Grass
38 *          Andreas Hansson
39 *          Sascha Bischoff
40 *          Neha Agarwal
41 */
42
43/**
44 * @file
45 * Declaration of DRAM rotation generator that rotates
46 * through each rank.
47 */
48
49#ifndef __CPU_TRAFFIC_GEN_DRAM_ROT_GEN_HH__
50#define __CPU_TRAFFIC_GEN_DRAM_ROT_GEN_HH__
51
52#include "base/bitfield.hh"
53#include "base/intmath.hh"
54#include "dram_gen.hh"
55#include "mem/packet.hh"
56
57class DramRotGen : public DramGen
58{
59
60  public:
61
62    /**
63     * Create a DRAM address sequence generator.
64     * This sequence generator will rotate through:
65     * 1) Banks per rank
66     * 2) Command type (if applicable)
67     * 3) Ranks per channel
68     *
69     * @param obj SimObject owning this sequence generator
70     * @param master_id MasterID related to the memory requests
71     * @param _duration duration of this state before transitioning
72     * @param start_addr Start address
73     * @param end_addr End address
74     * @param _blocksize Size used for transactions injected
75     * @param cacheline_size cache line size in the system
76     * @param min_period Lower limit of random inter-transaction time
77     * @param max_period Upper limit of random inter-transaction time
78     * @param read_percent Percent of transactions that are reads
79     * @param data_limit Upper limit on how much data to read/write
80     * @param num_seq_pkts Number of packets per stride, each of _blocksize
81     * @param page_size Page size (bytes) used in the DRAM
82     * @param nbr_of_banks_DRAM Total number of banks in DRAM
83     * @param nbr_of_banks_util Number of banks to utilized,
84     *                          for N banks, we will use banks: 0->(N-1)
85     * @param nbr_of_ranks Number of ranks utilized,
86     * @param addr_mapping Address mapping to be used,
87     *                     0: RoCoRaBaCh, 1: RoRaBaCoCh/RoRaBaChCo
88     *                     assumes single channel system
89     */
90    DramRotGen(SimObject &obj, MasterID master_id, Tick _duration,
91            Addr start_addr, Addr end_addr,
92            Addr _blocksize, Addr cacheline_size,
93            Tick min_period, Tick max_period,
94            uint8_t read_percent, Addr data_limit,
95            unsigned int num_seq_pkts, unsigned int page_size,
96            unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util,
97            unsigned int addr_mapping,
98            unsigned int nbr_of_ranks,
99            unsigned int max_seq_count_per_rank)
100        : DramGen(obj, master_id, _duration, start_addr, end_addr,
101          _blocksize, cacheline_size, min_period, max_period,
102          read_percent, data_limit,
103          num_seq_pkts, page_size, nbr_of_banks_DRAM,
104          nbr_of_banks_util, addr_mapping,
105          nbr_of_ranks),
106          maxSeqCountPerRank(max_seq_count_per_rank),
107          nextSeqCount(0)
108    {
109        // Rotating traffic generation can only support a read
110        // percentage of 0, 50, or 100
111        if (readPercent != 50  && readPercent != 100 && readPercent != 0) {
112           fatal("%s: Unsupported read percentage for DramRotGen: %d",
113                 _name, readPercent);
114        }
115    }
116
117    PacketPtr getNextPacket();
118
119  private:
120    /** Number of command series issued before the rank is
121        changed.  Should rotate to the next rank after rorating
122        throughall the banks for each specified command type     */
123    const unsigned int maxSeqCountPerRank;
124
125    /** Next packet series count used to set rank and bank,
126        and update isRead Incremented at the start of a new
127        packet series       */
128    unsigned int nextSeqCount;
129};
130
131#endif
132