dram_gen.hh revision 12396:3d04ea44fafb
1/* 2 * Copyright (c) 2012-2013, 2017 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed here under. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Thomas Grass 38 * Andreas Hansson 39 * Sascha Bischoff 40 * Neha Agarwal 41 */ 42 43/** 44 * @file 45 * Declaration of the DRAM generator for issuing variable page 46 * hit length requests and bank utilisation. 47 */ 48 49#ifndef __CPU_TRAFFIC_GEN_DRAM_GEN_HH__ 50#define __CPU_TRAFFIC_GEN_DRAM_GEN_HH__ 51 52#include "base/bitfield.hh" 53#include "base/intmath.hh" 54#include "mem/packet.hh" 55#include "proto/protoio.hh" 56#include "random_gen.hh" 57 58/** 59 * DRAM specific generator is for issuing request with variable page 60 * hit length and bank utilization. Currently assumes a single 61 * channel configuration. 62 */ 63class DramGen : public RandomGen 64{ 65 66 public: 67 68 /** 69 * Create a DRAM address sequence generator. 70 * 71 * @param _name Name to use for status and debug 72 * @param master_id MasterID set on each request 73 * @param _duration duration of this state before transitioning 74 * @param start_addr Start address 75 * @param end_addr End address 76 * @param _blocksize Size used for transactions injected 77 * @param min_period Lower limit of random inter-transaction time 78 * @param max_period Upper limit of random inter-transaction time 79 * @param read_percent Percent of transactions that are reads 80 * @param data_limit Upper limit on how much data to read/write 81 * @param num_seq_pkts Number of packets per stride, each of _blocksize 82 * @param page_size Page size (bytes) used in the DRAM 83 * @param nbr_of_banks_DRAM Total number of banks in DRAM 84 * @param nbr_of_banks_util Number of banks to utilized, 85 * for N banks, we will use banks: 0->(N-1) 86 * @param addr_mapping Address mapping to be used, 87 * 0: RoCoRaBaCh, 1: RoRaBaCoCh/RoRaBaChCo 88 * assumes single channel system 89 */ 90 DramGen(const std::string& _name, MasterID master_id, Tick _duration, 91 Addr start_addr, Addr end_addr, Addr _blocksize, 92 Tick min_period, Tick max_period, 93 uint8_t read_percent, Addr data_limit, 94 unsigned int num_seq_pkts, unsigned int page_size, 95 unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util, 96 unsigned int addr_mapping, 97 unsigned int nbr_of_ranks) 98 : RandomGen(_name, master_id, _duration, start_addr, end_addr, 99 _blocksize, min_period, max_period, read_percent, data_limit), 100 numSeqPkts(num_seq_pkts), countNumSeqPkts(0), addr(0), 101 isRead(true), pageSize(page_size), 102 pageBits(floorLog2(page_size / _blocksize)), 103 bankBits(floorLog2(nbr_of_banks_DRAM)), 104 blockBits(floorLog2(_blocksize)), 105 nbrOfBanksDRAM(nbr_of_banks_DRAM), 106 nbrOfBanksUtil(nbr_of_banks_util), addrMapping(addr_mapping), 107 rankBits(floorLog2(nbr_of_ranks)), 108 nbrOfRanks(nbr_of_ranks) 109 { 110 if (addrMapping != 1 && addrMapping != 0) { 111 addrMapping = 1; 112 warn("Unknown address mapping specified, using RoRaBaCoCh\n"); 113 } 114 } 115 116 PacketPtr getNextPacket(); 117 118 /** Insert bank, rank, and column bits into packed 119 * address to create address for 1st command in a 120 * series 121 * @param new_bank Bank number of next packet series 122 * @param new_rank Rank value of next packet series 123 */ 124 void genStartAddr(unsigned int new_bank , unsigned int new_rank); 125 126 protected: 127 128 /** Number of sequential DRAM packets to be generated per cpu request */ 129 const unsigned int numSeqPkts; 130 131 /** Track number of sequential packets generated for a request */ 132 unsigned int countNumSeqPkts; 133 134 /** Address of request */ 135 Addr addr; 136 137 /** Remember type of requests to be generated in series */ 138 bool isRead; 139 140 /** Page size of DRAM */ 141 const unsigned int pageSize; 142 143 /** Number of page bits in DRAM address */ 144 const unsigned int pageBits; 145 146 /** Number of bank bits in DRAM address*/ 147 const unsigned int bankBits; 148 149 /** Number of block bits in DRAM address */ 150 const unsigned int blockBits; 151 152 /** Number of banks in DRAM */ 153 const unsigned int nbrOfBanksDRAM; 154 155 /** Number of banks to be utilized for a given configuration */ 156 const unsigned int nbrOfBanksUtil; 157 158 /** Address mapping to be used */ 159 unsigned int addrMapping; 160 161 /** Number of rank bits in DRAM address*/ 162 const unsigned int rankBits; 163 164 /** Number of ranks to be utilized for a given configuration */ 165 const unsigned int nbrOfRanks; 166 167}; 168 169#endif 170