base_gen.hh revision 12844:c934a1338314 
1/*
2 * Copyright (c) 2012-2013, 2017-2018 ARM Limited
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4 *
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8 * to a hardware implementation of the functionality of the software
9 * licensed here under.  You may use the software subject to the license
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13 *
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15 * modification, are permitted provided that the following conditions are
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23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Thomas Grass
38 *          Andreas Hansson
39 *          Sascha Bischoff
40 *          Neha Agarwal
41 */
42
43/**
44 * @file
45 * Declaration of the base generator class for all generators.
46 */
47
48#ifndef __CPU_TRAFFIC_GEN_BASE_GEN_HH__
49#define __CPU_TRAFFIC_GEN_BASE_GEN_HH__
50
51#include "base/bitfield.hh"
52#include "base/intmath.hh"
53#include "mem/packet.hh"
54
55class BaseTrafficGen;
56
57/**
58 * Base class for all generators, with the shared functionality and
59 * virtual functions for entering, executing and leaving the
60 * generator.
61 */
62class BaseGen
63{
64
65  protected:
66
67    /** Name to use for status and debug printing */
68    const std::string _name;
69
70    /** The MasterID used for generating requests */
71    const MasterID masterID;
72
73    /**
74     * Generate a new request and associated packet
75     *
76     * @param addr Physical address to use
77     * @param size Size of the request
78     * @param cmd Memory command to send
79     * @param flags Optional request flags
80     */
81    PacketPtr getPacket(Addr addr, unsigned size, const MemCmd& cmd,
82                        Request::FlagsType flags = 0);
83
84  public:
85
86    /** Time to spend in this state */
87    const Tick duration;
88
89    /**
90     * Create a base generator.
91     *
92     * @param obj simobject owning the generator
93     * @param master_id MasterID set on each request
94     * @param _duration duration of this state before transitioning
95     */
96    BaseGen(SimObject &obj, MasterID master_id, Tick _duration);
97
98    virtual ~BaseGen() { }
99
100    /**
101     * Get the name, useful for DPRINTFs.
102     *
103     * @return the given name
104     */
105    std::string name() const { return _name; }
106
107    /**
108     * Enter this generator state.
109     */
110    virtual void enter() = 0;
111
112    /**
113     * Get the next generated packet.
114     *
115     * @return A packet to be sent at the current tick
116     */
117    virtual PacketPtr getNextPacket() = 0;
118
119    /**
120     * Exit this generator state. By default do nothing.
121     */
122    virtual void exit() { };
123
124    /**
125     * Determine the tick when the next packet is available. MaxTick
126     * means that there will not be any further packets in the current
127     * activation cycle of the generator.
128     *
129     * @param elastic should the injection respond to flow control or not
130     * @param delay time the previous packet spent waiting
131     * @return next tick when a packet is available
132     */
133    virtual Tick nextPacketTick(bool elastic, Tick delay) const = 0;
134
135};
136
137class StochasticGen : public BaseGen
138{
139  public:
140    StochasticGen(SimObject &obj,
141                  MasterID master_id, Tick _duration,
142                  Addr start_addr, Addr end_addr,
143                  Addr _blocksize, Addr cacheline_size,
144                  Tick min_period, Tick max_period,
145                  uint8_t read_percent, Addr data_limit);
146
147  protected:
148    /** Start of address range */
149    const Addr startAddr;
150
151    /** End of address range */
152    const Addr endAddr;
153
154    /** Blocksize and address increment */
155    const Addr blocksize;
156
157    /** Cache line size in the simulated system */
158    const Addr cacheLineSize;
159
160    /** Request generation period */
161    const Tick minPeriod;
162    const Tick maxPeriod;
163
164    /**
165     * Percent of generated transactions that should be reads
166     */
167    const uint8_t readPercent;
168
169    /** Maximum amount of data to manipulate */
170    const Addr dataLimit;
171};
172
173#endif
174