RubyTester.cc revision 9294
113992Stiago.muck@arm.com/* 213992Stiago.muck@arm.com * Copyright (c) 2012 ARM Limited 313992Stiago.muck@arm.com * All rights reserved 413992Stiago.muck@arm.com * 513992Stiago.muck@arm.com * The license below extends only to copyright in the software and shall 613992Stiago.muck@arm.com * not be construed as granting a license to any other intellectual 713992Stiago.muck@arm.com * property including but not limited to intellectual property relating 813992Stiago.muck@arm.com * to a hardware implementation of the functionality of the software 913992Stiago.muck@arm.com * licensed hereunder. You may use the software subject to the license 1013992Stiago.muck@arm.com * terms below provided that you ensure that this notice is replicated 1113992Stiago.muck@arm.com * unmodified and in its entirety in all distributions of the software, 1213992Stiago.muck@arm.com * modified or unmodified, in source code or in binary form. 1313992Stiago.muck@arm.com * 1413992Stiago.muck@arm.com * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 1513992Stiago.muck@arm.com * Copyright (c) 2009 Advanced Micro Devices, Inc. 1613992Stiago.muck@arm.com * All rights reserved. 1713992Stiago.muck@arm.com * 1813992Stiago.muck@arm.com * Redistribution and use in source and binary forms, with or without 1913992Stiago.muck@arm.com * modification, are permitted provided that the following conditions are 2013992Stiago.muck@arm.com * met: redistributions of source code must retain the above copyright 2113992Stiago.muck@arm.com * notice, this list of conditions and the following disclaimer; 2213992Stiago.muck@arm.com * redistributions in binary form must reproduce the above copyright 2313992Stiago.muck@arm.com * notice, this list of conditions and the following disclaimer in the 2413992Stiago.muck@arm.com * documentation and/or other materials provided with the distribution; 2513992Stiago.muck@arm.com * neither the name of the copyright holders nor the names of its 2613992Stiago.muck@arm.com * contributors may be used to endorse or promote products derived from 2713992Stiago.muck@arm.com * this software without specific prior written permission. 2813992Stiago.muck@arm.com * 2913992Stiago.muck@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3013992Stiago.muck@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3113992Stiago.muck@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3213992Stiago.muck@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3313992Stiago.muck@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3413992Stiago.muck@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3513992Stiago.muck@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3613992Stiago.muck@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3713992Stiago.muck@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3813992Stiago.muck@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3913992Stiago.muck@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4013992Stiago.muck@arm.com */ 4113992Stiago.muck@arm.com 4213992Stiago.muck@arm.com#include "base/misc.hh" 4313992Stiago.muck@arm.com#include "cpu/testers/rubytest/Check.hh" 4413992Stiago.muck@arm.com#include "cpu/testers/rubytest/RubyTester.hh" 4513992Stiago.muck@arm.com#include "debug/RubyTest.hh" 4613992Stiago.muck@arm.com#include "mem/ruby/common/Global.hh" 4713992Stiago.muck@arm.com#include "mem/ruby/common/SubBlock.hh" 4813992Stiago.muck@arm.com#include "mem/ruby/system/System.hh" 4913992Stiago.muck@arm.com#include "sim/sim_exit.hh" 5013992Stiago.muck@arm.com#include "sim/system.hh" 5113992Stiago.muck@arm.com 5213992Stiago.muck@arm.comRubyTester::RubyTester(const Params *p) 5313992Stiago.muck@arm.com : MemObject(p), checkStartEvent(this), 5413992Stiago.muck@arm.com _masterId(p->system->getMasterId(name())), 5513992Stiago.muck@arm.com m_num_cpus(p->num_cpus), 5613992Stiago.muck@arm.com m_checks_to_complete(p->checks_to_complete), 5713992Stiago.muck@arm.com m_deadlock_threshold(p->deadlock_threshold), 5813992Stiago.muck@arm.com m_wakeup_frequency(p->wakeup_frequency), 5913992Stiago.muck@arm.com m_check_flush(p->check_flush), 6013992Stiago.muck@arm.com m_num_inst_ports(p->port_cpuInstPort_connection_count) 6113992Stiago.muck@arm.com{ 6213992Stiago.muck@arm.com m_checks_completed = 0; 6313992Stiago.muck@arm.com 6413992Stiago.muck@arm.com // 6513992Stiago.muck@arm.com // Create the requested inst and data ports and place them on the 6613992Stiago.muck@arm.com // appropriate read and write port lists. The reason for the subtle 6713992Stiago.muck@arm.com // difference between inst and data ports vs. read and write ports is 6813992Stiago.muck@arm.com // from the tester's perspective, it only needs to know whether a port 6913992Stiago.muck@arm.com // supports reads (checks) or writes (actions). Meanwhile, the protocol 7013992Stiago.muck@arm.com // controllers have data ports (support read and writes) or inst ports 7113992Stiago.muck@arm.com // (support only reads). 7213992Stiago.muck@arm.com // Note: the inst ports are the lowest elements of the readPort vector, 7313992Stiago.muck@arm.com // then the data ports are added to the readPort vector 7413992Stiago.muck@arm.com // 7513992Stiago.muck@arm.com for (int i = 0; i < p->port_cpuInstPort_connection_count; ++i) { 7613992Stiago.muck@arm.com readPorts.push_back(new CpuPort(csprintf("%s-instPort%d", name(), i), 7713992Stiago.muck@arm.com this, i)); 7813992Stiago.muck@arm.com } 7913992Stiago.muck@arm.com for (int i = 0; i < p->port_cpuDataPort_connection_count; ++i) { 8013992Stiago.muck@arm.com CpuPort *port = new CpuPort(csprintf("%s-dataPort%d", name(), i), 8113992Stiago.muck@arm.com this, i); 8213992Stiago.muck@arm.com readPorts.push_back(port); 8313992Stiago.muck@arm.com writePorts.push_back(port); 8413992Stiago.muck@arm.com } 8513992Stiago.muck@arm.com 8613992Stiago.muck@arm.com // add the check start event to the event queue 8713992Stiago.muck@arm.com schedule(checkStartEvent, 1); 8813992Stiago.muck@arm.com} 8913992Stiago.muck@arm.com 9013992Stiago.muck@arm.comRubyTester::~RubyTester() 9113992Stiago.muck@arm.com{ 9213992Stiago.muck@arm.com delete m_checkTable_ptr; 9313992Stiago.muck@arm.com // Only delete the readPorts since the writePorts are just a subset 9413992Stiago.muck@arm.com for (int i = 0; i < readPorts.size(); i++) 9513992Stiago.muck@arm.com delete readPorts[i]; 9613992Stiago.muck@arm.com} 9713992Stiago.muck@arm.com 9813992Stiago.muck@arm.comvoid 9913992Stiago.muck@arm.comRubyTester::init() 10013992Stiago.muck@arm.com{ 10113992Stiago.muck@arm.com assert(writePorts.size() > 0 && readPorts.size() > 0); 10213992Stiago.muck@arm.com 10313992Stiago.muck@arm.com m_last_progress_vector.resize(m_num_cpus); 10413992Stiago.muck@arm.com for (int i = 0; i < m_last_progress_vector.size(); i++) { 10513992Stiago.muck@arm.com m_last_progress_vector[i] = 0; 10613992Stiago.muck@arm.com } 10713992Stiago.muck@arm.com 10813992Stiago.muck@arm.com m_num_writers = writePorts.size(); 10913992Stiago.muck@arm.com m_num_readers = readPorts.size(); 11013992Stiago.muck@arm.com 11113992Stiago.muck@arm.com m_checkTable_ptr = new CheckTable(m_num_writers, m_num_readers, this); 11213992Stiago.muck@arm.com} 11313992Stiago.muck@arm.com 11413992Stiago.muck@arm.comBaseMasterPort & 11513992Stiago.muck@arm.comRubyTester::getMasterPort(const std::string &if_name, PortID idx) 11613992Stiago.muck@arm.com{ 11713992Stiago.muck@arm.com if (if_name != "cpuInstPort" && if_name != "cpuDataPort") { 11813992Stiago.muck@arm.com // pass it along to our super class 11913992Stiago.muck@arm.com return MemObject::getMasterPort(if_name, idx); 12013992Stiago.muck@arm.com } else { 12113992Stiago.muck@arm.com if (if_name == "cpuInstPort") { 12213992Stiago.muck@arm.com if (idx > m_num_inst_ports) { 12313992Stiago.muck@arm.com panic("RubyTester::getMasterPort: unknown inst port idx %d\n", 12413992Stiago.muck@arm.com idx); 12513992Stiago.muck@arm.com } 12613992Stiago.muck@arm.com // 12713992Stiago.muck@arm.com // inst ports directly map to the lowest readPort elements 12813992Stiago.muck@arm.com // 12913992Stiago.muck@arm.com return *readPorts[idx]; 13013992Stiago.muck@arm.com } else { 13113992Stiago.muck@arm.com assert(if_name == "cpuDataPort"); 13213992Stiago.muck@arm.com // 13313992Stiago.muck@arm.com // add the inst port offset to translate to the correct read port 13413992Stiago.muck@arm.com // index 13513992Stiago.muck@arm.com // 13613992Stiago.muck@arm.com int read_idx = idx + m_num_inst_ports; 137 if (read_idx >= static_cast<PortID>(readPorts.size())) { 138 panic("RubyTester::getMasterPort: unknown data port idx %d\n", 139 idx); 140 } 141 return *readPorts[read_idx]; 142 } 143 } 144} 145 146bool 147RubyTester::CpuPort::recvTimingResp(PacketPtr pkt) 148{ 149 // retrieve the subblock and call hitCallback 150 RubyTester::SenderState* senderState = 151 safe_cast<RubyTester::SenderState*>(pkt->senderState); 152 SubBlock* subblock = senderState->subBlock; 153 assert(subblock != NULL); 154 155 // pop the sender state from the packet 156 pkt->senderState = senderState->saved; 157 158 tester->hitCallback(id, subblock); 159 160 // Now that the tester has completed, delete the senderState 161 // (includes sublock) and the packet, then return 162 delete senderState; 163 delete pkt->req; 164 delete pkt; 165 return true; 166} 167 168bool 169RubyTester::isInstReadableCpuPort(int idx) 170{ 171 return idx < m_num_inst_ports; 172} 173 174MasterPort* 175RubyTester::getReadableCpuPort(int idx) 176{ 177 assert(idx >= 0 && idx < readPorts.size()); 178 179 return readPorts[idx]; 180} 181 182MasterPort* 183RubyTester::getWritableCpuPort(int idx) 184{ 185 assert(idx >= 0 && idx < writePorts.size()); 186 187 return writePorts[idx]; 188} 189 190void 191RubyTester::hitCallback(NodeID proc, SubBlock* data) 192{ 193 // Mark that we made progress 194 m_last_progress_vector[proc] = g_system_ptr->getTime(); 195 196 DPRINTF(RubyTest, "completed request for proc: %d\n", proc); 197 DPRINTF(RubyTest, "addr: 0x%x, size: %d, data: ", 198 data->getAddress(), data->getSize()); 199 for (int byte = 0; byte < data->getSize(); byte++) { 200 DPRINTF(RubyTest, "%d", data->getByte(byte)); 201 } 202 DPRINTF(RubyTest, "\n"); 203 204 // This tells us our store has 'completed' or for a load gives us 205 // back the data to make the check 206 Check* check_ptr = m_checkTable_ptr->getCheck(data->getAddress()); 207 assert(check_ptr != NULL); 208 check_ptr->performCallback(proc, data); 209} 210 211void 212RubyTester::wakeup() 213{ 214 if (m_checks_completed < m_checks_to_complete) { 215 // Try to perform an action or check 216 Check* check_ptr = m_checkTable_ptr->getRandomCheck(); 217 assert(check_ptr != NULL); 218 check_ptr->initiate(); 219 220 checkForDeadlock(); 221 222 schedule(checkStartEvent, curTick() + m_wakeup_frequency); 223 } else { 224 exitSimLoop("Ruby Tester completed"); 225 } 226} 227 228void 229RubyTester::checkForDeadlock() 230{ 231 int size = m_last_progress_vector.size(); 232 Time current_time = g_system_ptr->getTime(); 233 for (int processor = 0; processor < size; processor++) { 234 if ((current_time - m_last_progress_vector[processor]) > 235 m_deadlock_threshold) { 236 panic("Deadlock detected: current_time: %d last_progress_time: %d " 237 "difference: %d processor: %d\n", 238 current_time, m_last_progress_vector[processor], 239 current_time - m_last_progress_vector[processor], processor); 240 } 241 } 242} 243 244void 245RubyTester::print(std::ostream& out) const 246{ 247 out << "[RubyTester]" << std::endl; 248} 249 250RubyTester * 251RubyTesterParams::create() 252{ 253 return new RubyTester(this); 254} 255