RubyTester.cc revision 12129
12207SN/A/* 25254Sksewell@umich.edu * Copyright (c) 2012-2013 ARM Limited 35254Sksewell@umich.edu * All rights reserved 42207SN/A * 55254Sksewell@umich.edu * The license below extends only to copyright in the software and shall 65254Sksewell@umich.edu * not be construed as granting a license to any other intellectual 75254Sksewell@umich.edu * property including but not limited to intellectual property relating 85254Sksewell@umich.edu * to a hardware implementation of the functionality of the software 95254Sksewell@umich.edu * licensed hereunder. You may use the software subject to the license 105254Sksewell@umich.edu * terms below provided that you ensure that this notice is replicated 115254Sksewell@umich.edu * unmodified and in its entirety in all distributions of the software, 125254Sksewell@umich.edu * modified or unmodified, in source code or in binary form. 135254Sksewell@umich.edu * 145254Sksewell@umich.edu * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 152207SN/A * Copyright (c) 2009 Advanced Micro Devices, Inc. 165254Sksewell@umich.edu * All rights reserved. 175254Sksewell@umich.edu * 185254Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 195254Sksewell@umich.edu * modification, are permitted provided that the following conditions are 205254Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 215254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 225254Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 235254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 245254Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 255254Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 265254Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 272665Ssaidi@eecs.umich.edu * this software without specific prior written permission. 285254Sksewell@umich.edu * 295254Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 305254Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312207SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322207SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3311793Sbrandon.potter@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3411793Sbrandon.potter@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352474SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 368229Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372454SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3812334Sgabeblack@google.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392680Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 408232Snate@binkert.org */ 416650Sksewell@umich.edu 4211854Sbrandon.potter@amd.com#include "cpu/testers/rubytest/RubyTester.hh" 436650Sksewell@umich.edu 446650Sksewell@umich.edu#include "base/misc.hh" 4511800Sbrandon.potter@amd.com#include "base/trace.hh" 462474SN/A#include "cpu/testers/rubytest/Check.hh" 472207SN/A#include "debug/RubyTest.hh" 482447SN/A#include "mem/ruby/common/SubBlock.hh" 492474SN/A#include "sim/sim_exit.hh" 502447SN/A#include "sim/system.hh" 5111851Sbrandon.potter@amd.com 5211851Sbrandon.potter@amd.comRubyTester::RubyTester(const Params *p) 532474SN/A : MemObject(p), 542686Sksewell@umich.edu checkStartEvent([this]{ wakeup(); }, "RubyTester tick", 552686Sksewell@umich.edu false, Event::CPU_Tick_Pri), 5611905SBrandon.Potter@amd.com _masterId(p->system->getMasterId(name())), 5711905SBrandon.Potter@amd.com m_checkTable_ptr(nullptr), 5811905SBrandon.Potter@amd.com m_num_cpus(p->num_cpus), 592474SN/A m_checks_to_complete(p->checks_to_complete), 602474SN/A m_deadlock_threshold(p->deadlock_threshold), 6111905SBrandon.Potter@amd.com m_num_writers(0), 622474SN/A m_num_readers(0), 632686Sksewell@umich.edu m_wakeup_frequency(p->wakeup_frequency), 6411905SBrandon.Potter@amd.com m_check_flush(p->check_flush), 6511905SBrandon.Potter@amd.com m_num_inst_only_ports(p->port_cpuInstPort_connection_count), 6611905SBrandon.Potter@amd.com m_num_inst_data_ports(p->port_cpuInstDataPort_connection_count) 672686Sksewell@umich.edu{ 686811SMatt DeVuyst m_checks_completed = 0; 6911905SBrandon.Potter@amd.com 7011905SBrandon.Potter@amd.com // 7111905SBrandon.Potter@amd.com // Create the requested inst and data ports and place them on the 7211905SBrandon.Potter@amd.com // appropriate read and write port lists. The reason for the subtle 732474SN/A // difference between inst and data ports vs. read and write ports is 742474SN/A // from the tester's perspective, it only needs to know whether a port 752474SN/A // supports reads (checks) or writes (actions). Meanwhile, the protocol 7611851Sbrandon.potter@amd.com // controllers have data ports (support read and writes) or inst ports 772474SN/A // (support only reads). 7811851Sbrandon.potter@amd.com // Note: the inst ports are the lowest elements of the readPort vector, 796650Sksewell@umich.edu // then the data ports are added to the readPort vector 8010318Sandreas.hansson@arm.com // 812474SN/A int idx = 0; 825958Sgblack@eecs.umich.edu for (int i = 0; i < p->port_cpuInstPort_connection_count; ++i) { 836811SMatt DeVuyst readPorts.push_back(new CpuPort(csprintf("%s-instPort%d", name(), i), 846650Sksewell@umich.edu this, i, idx)); 8511851Sbrandon.potter@amd.com idx++; 866650Sksewell@umich.edu } 876811SMatt DeVuyst for (int i = 0; i < p->port_cpuInstDataPort_connection_count; ++i) { 886811SMatt DeVuyst CpuPort *port = new CpuPort(csprintf("%s-instDataPort%d", name(), i), 8911389Sbrandon.potter@amd.com this, i, idx); 9011389Sbrandon.potter@amd.com readPorts.push_back(port); 9111389Sbrandon.potter@amd.com writePorts.push_back(port); 926650Sksewell@umich.edu idx++; 936650Sksewell@umich.edu } 946650Sksewell@umich.edu for (int i = 0; i < p->port_cpuDataPort_connection_count; ++i) { 956811SMatt DeVuyst CpuPort *port = new CpuPort(csprintf("%s-dataPort%d", name(), i), 966811SMatt DeVuyst this, i, idx); 976811SMatt DeVuyst readPorts.push_back(port); 986811SMatt DeVuyst writePorts.push_back(port); 996811SMatt DeVuyst idx++; 1006811SMatt DeVuyst } 1016811SMatt DeVuyst 10210318Sandreas.hansson@arm.com // add the check start event to the event queue 1036811SMatt DeVuyst schedule(checkStartEvent, 1); 1046811SMatt DeVuyst} 1056811SMatt DeVuyst 1066811SMatt DeVuystRubyTester::~RubyTester() 1076811SMatt DeVuyst{ 1086811SMatt DeVuyst delete m_checkTable_ptr; 1096811SMatt DeVuyst // Only delete the readPorts since the writePorts are just a subset 1106811SMatt DeVuyst for (int i = 0; i < readPorts.size(); i++) 1116811SMatt DeVuyst delete readPorts[i]; 1126811SMatt DeVuyst} 1136811SMatt DeVuyst 11411389Sbrandon.potter@amd.comvoid 11511389Sbrandon.potter@amd.comRubyTester::init() 11611389Sbrandon.potter@amd.com{ 11711389Sbrandon.potter@amd.com assert(writePorts.size() > 0 && readPorts.size() > 0); 1186811SMatt DeVuyst 1196811SMatt DeVuyst m_last_progress_vector.resize(m_num_cpus); 1206811SMatt DeVuyst for (int i = 0; i < m_last_progress_vector.size(); i++) { 1216811SMatt DeVuyst m_last_progress_vector[i] = Cycles(0); 1226811SMatt DeVuyst } 1236811SMatt DeVuyst 1246811SMatt DeVuyst m_num_writers = writePorts.size(); 1256811SMatt DeVuyst m_num_readers = readPorts.size(); 1266811SMatt DeVuyst assert(m_num_readers == m_num_cpus); 1276811SMatt DeVuyst 1286650Sksewell@umich.edu m_checkTable_ptr = new CheckTable(m_num_writers, m_num_readers, this); 1296650Sksewell@umich.edu} 1306811SMatt DeVuyst 1316811SMatt DeVuystBaseMasterPort & 1326650Sksewell@umich.eduRubyTester::getMasterPort(const std::string &if_name, PortID idx) 1336650Sksewell@umich.edu{ 1346650Sksewell@umich.edu if (if_name != "cpuInstPort" && if_name != "cpuInstDataPort" && 1356650Sksewell@umich.edu if_name != "cpuDataPort") { 1366650Sksewell@umich.edu // pass it along to our super class 1376650Sksewell@umich.edu return MemObject::getMasterPort(if_name, idx); 1386650Sksewell@umich.edu } else { 1396650Sksewell@umich.edu if (if_name == "cpuInstPort") { 1406650Sksewell@umich.edu if (idx > m_num_inst_only_ports) { 1416650Sksewell@umich.edu panic("RubyTester::getMasterPort: unknown inst port %d\n", 1426811SMatt DeVuyst idx); 1436811SMatt DeVuyst } 1446811SMatt DeVuyst // 1456811SMatt DeVuyst // inst ports map to the lowest readPort elements 1466811SMatt DeVuyst // 1476650Sksewell@umich.edu return *readPorts[idx]; 1486650Sksewell@umich.edu } else if (if_name == "cpuInstDataPort") { 14911905SBrandon.Potter@amd.com if (idx > m_num_inst_data_ports) { 1506650Sksewell@umich.edu panic("RubyTester::getMasterPort: unknown inst+data port %d\n", 15111905SBrandon.Potter@amd.com idx); 15211905SBrandon.Potter@amd.com } 1536650Sksewell@umich.edu int read_idx = idx + m_num_inst_only_ports; 15411905SBrandon.Potter@amd.com // 15511905SBrandon.Potter@amd.com // inst+data ports map to the next readPort elements 1566650Sksewell@umich.edu // 15711905SBrandon.Potter@amd.com return *readPorts[read_idx]; 15811905SBrandon.Potter@amd.com } else { 1596811SMatt DeVuyst assert(if_name == "cpuDataPort"); 1606811SMatt DeVuyst // 1616811SMatt DeVuyst // data only ports map to the final readPort elements 1626811SMatt DeVuyst // 1636650Sksewell@umich.edu if (idx > (static_cast<int>(readPorts.size()) - 1646650Sksewell@umich.edu (m_num_inst_only_ports + m_num_inst_data_ports))) { 1656811SMatt DeVuyst panic("RubyTester::getMasterPort: unknown data port %d\n", 1666650Sksewell@umich.edu idx); 1676811SMatt DeVuyst } 1686650Sksewell@umich.edu int read_idx = idx + m_num_inst_only_ports + m_num_inst_data_ports; 16911905SBrandon.Potter@amd.com return *readPorts[read_idx]; 1706650Sksewell@umich.edu } 1716650Sksewell@umich.edu // Note: currently the Ruby Tester does not support write only ports 1726650Sksewell@umich.edu // but that could easily be added here 1736650Sksewell@umich.edu } 1746650Sksewell@umich.edu} 1756811SMatt DeVuyst 1766811SMatt DeVuystbool 1778852Sandreas.hansson@arm.comRubyTester::CpuPort::recvTimingResp(PacketPtr pkt) 1786811SMatt DeVuyst{ 1798852Sandreas.hansson@arm.com // retrieve the subblock and call hitCallback 1806811SMatt DeVuyst RubyTester::SenderState* senderState = 1816811SMatt DeVuyst safe_cast<RubyTester::SenderState*>(pkt->senderState); 1826811SMatt DeVuyst SubBlock& subblock = senderState->subBlock; 1836811SMatt DeVuyst 1846811SMatt DeVuyst tester->hitCallback(globalIdx, &subblock); 1856811SMatt DeVuyst 1866811SMatt DeVuyst // Now that the tester has completed, delete the senderState 1878852Sandreas.hansson@arm.com // (includes sublock) and the packet, then return 1886811SMatt DeVuyst delete pkt->senderState; 1896811SMatt DeVuyst delete pkt->req; 1906650Sksewell@umich.edu delete pkt; 1916650Sksewell@umich.edu return true; 1926650Sksewell@umich.edu} 1936650Sksewell@umich.edu 19411905SBrandon.Potter@amd.combool 1956650Sksewell@umich.eduRubyTester::isInstOnlyCpuPort(int idx) 19611389Sbrandon.potter@amd.com{ 1976650Sksewell@umich.edu return idx < m_num_inst_only_ports; 1986650Sksewell@umich.edu} 1996650Sksewell@umich.edu 2005958Sgblack@eecs.umich.edubool 20111851Sbrandon.potter@amd.comRubyTester::isInstDataCpuPort(int idx) 2025958Sgblack@eecs.umich.edu{ 2035958Sgblack@eecs.umich.edu return ((idx >= m_num_inst_only_ports) && 2046701Sgblack@eecs.umich.edu (idx < (m_num_inst_only_ports + m_num_inst_data_ports))); 2055958Sgblack@eecs.umich.edu} 2065958Sgblack@eecs.umich.edu 2075958Sgblack@eecs.umich.eduMasterPort* 20811851Sbrandon.potter@amd.comRubyTester::getReadableCpuPort(int idx) 2095958Sgblack@eecs.umich.edu{ 2105958Sgblack@eecs.umich.edu assert(idx >= 0 && idx < readPorts.size()); 2115958Sgblack@eecs.umich.edu 2125958Sgblack@eecs.umich.edu return readPorts[idx]; 2135958Sgblack@eecs.umich.edu} 2145958Sgblack@eecs.umich.edu 21511851Sbrandon.potter@amd.comMasterPort* 2165958Sgblack@eecs.umich.eduRubyTester::getWritableCpuPort(int idx) 21710223Ssteve.reinhardt@amd.com{ 2185958Sgblack@eecs.umich.edu assert(idx >= 0 && idx < writePorts.size()); 2195958Sgblack@eecs.umich.edu 22010223Ssteve.reinhardt@amd.com return writePorts[idx]; 2215958Sgblack@eecs.umich.edu} 2225958Sgblack@eecs.umich.edu 2235958Sgblack@eecs.umich.eduvoid 22410223Ssteve.reinhardt@amd.comRubyTester::hitCallback(NodeID proc, SubBlock* data) 2255958Sgblack@eecs.umich.edu{ 2265958Sgblack@eecs.umich.edu // Mark that we made progress 227 m_last_progress_vector[proc] = curCycle(); 228 229 DPRINTF(RubyTest, "completed request for proc: %d", proc); 230 DPRINTFR(RubyTest, " addr: 0x%x, size: %d, data: ", 231 data->getAddress(), data->getSize()); 232 for (int byte = 0; byte < data->getSize(); byte++) { 233 DPRINTFR(RubyTest, "%d ", data->getByte(byte)); 234 } 235 DPRINTFR(RubyTest, "\n"); 236 237 // This tells us our store has 'completed' or for a load gives us 238 // back the data to make the check 239 Check* check_ptr = m_checkTable_ptr->getCheck(data->getAddress()); 240 assert(check_ptr != NULL); 241 check_ptr->performCallback(proc, data, curCycle()); 242} 243 244void 245RubyTester::wakeup() 246{ 247 if (m_checks_completed < m_checks_to_complete) { 248 // Try to perform an action or check 249 Check* check_ptr = m_checkTable_ptr->getRandomCheck(); 250 assert(check_ptr != NULL); 251 check_ptr->initiate(); 252 253 checkForDeadlock(); 254 255 schedule(checkStartEvent, curTick() + m_wakeup_frequency); 256 } else { 257 exitSimLoop("Ruby Tester completed"); 258 } 259} 260 261void 262RubyTester::checkForDeadlock() 263{ 264 int size = m_last_progress_vector.size(); 265 Cycles current_time = curCycle(); 266 for (int processor = 0; processor < size; processor++) { 267 if ((current_time - m_last_progress_vector[processor]) > 268 m_deadlock_threshold) { 269 panic("Deadlock detected: current_time: %d last_progress_time: %d " 270 "difference: %d processor: %d\n", 271 current_time, m_last_progress_vector[processor], 272 current_time - m_last_progress_vector[processor], processor); 273 } 274 } 275} 276 277void 278RubyTester::print(std::ostream& out) const 279{ 280 out << "[RubyTester]" << std::endl; 281} 282 283RubyTester * 284RubyTesterParams::create() 285{ 286 return new RubyTester(this); 287} 288