RubyTester.cc revision 11793
16899SN/A/* 29542Sandreas.hansson@arm.com * Copyright (c) 2012-2013 ARM Limited 38851Sandreas.hansson@arm.com * All rights reserved 48851Sandreas.hansson@arm.com * 58851Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68851Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78851Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88851Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98851Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108851Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118851Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128851Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138851Sandreas.hansson@arm.com * 146899SN/A * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 156899SN/A * Copyright (c) 2009 Advanced Micro Devices, Inc. 166899SN/A * All rights reserved. 176899SN/A * 186899SN/A * Redistribution and use in source and binary forms, with or without 196899SN/A * modification, are permitted provided that the following conditions are 206899SN/A * met: redistributions of source code must retain the above copyright 216899SN/A * notice, this list of conditions and the following disclaimer; 226899SN/A * redistributions in binary form must reproduce the above copyright 236899SN/A * notice, this list of conditions and the following disclaimer in the 246899SN/A * documentation and/or other materials provided with the distribution; 256899SN/A * neither the name of the copyright holders nor the names of its 266899SN/A * contributors may be used to endorse or promote products derived from 276899SN/A * this software without specific prior written permission. 286899SN/A * 296899SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306899SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316899SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326899SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336899SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346899SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356899SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366899SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376899SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386899SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396899SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406899SN/A */ 416899SN/A 4211793Sbrandon.potter@amd.com#include "cpu/testers/rubytest/RubyTester.hh" 4311793Sbrandon.potter@amd.com 447805Snilay@cs.wisc.edu#include "base/misc.hh" 457632SBrad.Beckmann@amd.com#include "cpu/testers/rubytest/Check.hh" 468232Snate@binkert.org#include "debug/RubyTest.hh" 477053SN/A#include "mem/ruby/common/SubBlock.hh" 486899SN/A#include "sim/sim_exit.hh" 498832SAli.Saidi@ARM.com#include "sim/system.hh" 506899SN/A 516899SN/ARubyTester::RubyTester(const Params *p) 527053SN/A : MemObject(p), checkStartEvent(this), 538832SAli.Saidi@ARM.com _masterId(p->system->getMasterId(name())), 5410412Sandreas.hansson@arm.com m_checkTable_ptr(nullptr), 558932SBrad.Beckmann@amd.com m_num_cpus(p->num_cpus), 566899SN/A m_checks_to_complete(p->checks_to_complete), 576899SN/A m_deadlock_threshold(p->deadlock_threshold), 5810412Sandreas.hansson@arm.com m_num_writers(0), 5910412Sandreas.hansson@arm.com m_num_readers(0), 608184Ssomayeh@cs.wisc.edu m_wakeup_frequency(p->wakeup_frequency), 618932SBrad.Beckmann@amd.com m_check_flush(p->check_flush), 6211266SBrad.Beckmann@amd.com m_num_inst_only_ports(p->port_cpuInstPort_connection_count), 6311266SBrad.Beckmann@amd.com m_num_inst_data_ports(p->port_cpuInstDataPort_connection_count) 646899SN/A{ 657053SN/A m_checks_completed = 0; 666899SN/A 678932SBrad.Beckmann@amd.com // 688932SBrad.Beckmann@amd.com // Create the requested inst and data ports and place them on the 698932SBrad.Beckmann@amd.com // appropriate read and write port lists. The reason for the subtle 708932SBrad.Beckmann@amd.com // difference between inst and data ports vs. read and write ports is 718932SBrad.Beckmann@amd.com // from the tester's perspective, it only needs to know whether a port 728932SBrad.Beckmann@amd.com // supports reads (checks) or writes (actions). Meanwhile, the protocol 738932SBrad.Beckmann@amd.com // controllers have data ports (support read and writes) or inst ports 748932SBrad.Beckmann@amd.com // (support only reads). 758932SBrad.Beckmann@amd.com // Note: the inst ports are the lowest elements of the readPort vector, 768932SBrad.Beckmann@amd.com // then the data ports are added to the readPort vector 778932SBrad.Beckmann@amd.com // 7811266SBrad.Beckmann@amd.com int idx = 0; 798932SBrad.Beckmann@amd.com for (int i = 0; i < p->port_cpuInstPort_connection_count; ++i) { 808932SBrad.Beckmann@amd.com readPorts.push_back(new CpuPort(csprintf("%s-instPort%d", name(), i), 8111266SBrad.Beckmann@amd.com this, i, idx)); 8211266SBrad.Beckmann@amd.com idx++; 8311266SBrad.Beckmann@amd.com } 8411266SBrad.Beckmann@amd.com for (int i = 0; i < p->port_cpuInstDataPort_connection_count; ++i) { 8511266SBrad.Beckmann@amd.com CpuPort *port = new CpuPort(csprintf("%s-instDataPort%d", name(), i), 8611266SBrad.Beckmann@amd.com this, i, idx); 8711266SBrad.Beckmann@amd.com readPorts.push_back(port); 8811266SBrad.Beckmann@amd.com writePorts.push_back(port); 8911266SBrad.Beckmann@amd.com idx++; 908932SBrad.Beckmann@amd.com } 918932SBrad.Beckmann@amd.com for (int i = 0; i < p->port_cpuDataPort_connection_count; ++i) { 928950Sandreas.hansson@arm.com CpuPort *port = new CpuPort(csprintf("%s-dataPort%d", name(), i), 9311266SBrad.Beckmann@amd.com this, i, idx); 948932SBrad.Beckmann@amd.com readPorts.push_back(port); 958932SBrad.Beckmann@amd.com writePorts.push_back(port); 9611266SBrad.Beckmann@amd.com idx++; 978851Sandreas.hansson@arm.com } 988851Sandreas.hansson@arm.com 997053SN/A // add the check start event to the event queue 1007053SN/A schedule(checkStartEvent, 1); 1016899SN/A} 1026899SN/A 1036899SN/ARubyTester::~RubyTester() 1046899SN/A{ 1057053SN/A delete m_checkTable_ptr; 1068932SBrad.Beckmann@amd.com // Only delete the readPorts since the writePorts are just a subset 1078932SBrad.Beckmann@amd.com for (int i = 0; i < readPorts.size(); i++) 1088932SBrad.Beckmann@amd.com delete readPorts[i]; 1096899SN/A} 1106899SN/A 1117053SN/Avoid 1127053SN/ARubyTester::init() 1136899SN/A{ 1148932SBrad.Beckmann@amd.com assert(writePorts.size() > 0 && readPorts.size() > 0); 1156899SN/A 1168932SBrad.Beckmann@amd.com m_last_progress_vector.resize(m_num_cpus); 1177053SN/A for (int i = 0; i < m_last_progress_vector.size(); i++) { 11810302Snilay@cs.wisc.edu m_last_progress_vector[i] = Cycles(0); 1197053SN/A } 1206899SN/A 1218932SBrad.Beckmann@amd.com m_num_writers = writePorts.size(); 1228932SBrad.Beckmann@amd.com m_num_readers = readPorts.size(); 12311266SBrad.Beckmann@amd.com assert(m_num_readers == m_num_cpus); 1246899SN/A 1258932SBrad.Beckmann@amd.com m_checkTable_ptr = new CheckTable(m_num_writers, m_num_readers, this); 1266899SN/A} 1276899SN/A 1289294Sandreas.hansson@arm.comBaseMasterPort & 1299294Sandreas.hansson@arm.comRubyTester::getMasterPort(const std::string &if_name, PortID idx) 1306899SN/A{ 13111266SBrad.Beckmann@amd.com if (if_name != "cpuInstPort" && if_name != "cpuInstDataPort" && 13211266SBrad.Beckmann@amd.com if_name != "cpuDataPort") { 1338922Swilliam.wang@arm.com // pass it along to our super class 1348922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 1358922Swilliam.wang@arm.com } else { 1368932SBrad.Beckmann@amd.com if (if_name == "cpuInstPort") { 13711266SBrad.Beckmann@amd.com if (idx > m_num_inst_only_ports) { 13811266SBrad.Beckmann@amd.com panic("RubyTester::getMasterPort: unknown inst port %d\n", 1398932SBrad.Beckmann@amd.com idx); 1408932SBrad.Beckmann@amd.com } 1418932SBrad.Beckmann@amd.com // 14211266SBrad.Beckmann@amd.com // inst ports map to the lowest readPort elements 1438932SBrad.Beckmann@amd.com // 1448932SBrad.Beckmann@amd.com return *readPorts[idx]; 14511266SBrad.Beckmann@amd.com } else if (if_name == "cpuInstDataPort") { 14611266SBrad.Beckmann@amd.com if (idx > m_num_inst_data_ports) { 14711266SBrad.Beckmann@amd.com panic("RubyTester::getMasterPort: unknown inst+data port %d\n", 14811266SBrad.Beckmann@amd.com idx); 14911266SBrad.Beckmann@amd.com } 15011266SBrad.Beckmann@amd.com int read_idx = idx + m_num_inst_only_ports; 15111266SBrad.Beckmann@amd.com // 15211266SBrad.Beckmann@amd.com // inst+data ports map to the next readPort elements 15311266SBrad.Beckmann@amd.com // 15411266SBrad.Beckmann@amd.com return *readPorts[read_idx]; 1558932SBrad.Beckmann@amd.com } else { 1568932SBrad.Beckmann@amd.com assert(if_name == "cpuDataPort"); 1578932SBrad.Beckmann@amd.com // 15811266SBrad.Beckmann@amd.com // data only ports map to the final readPort elements 1598932SBrad.Beckmann@amd.com // 16011266SBrad.Beckmann@amd.com if (idx > (static_cast<int>(readPorts.size()) - 16111266SBrad.Beckmann@amd.com (m_num_inst_only_ports + m_num_inst_data_ports))) { 16211266SBrad.Beckmann@amd.com panic("RubyTester::getMasterPort: unknown data port %d\n", 1638932SBrad.Beckmann@amd.com idx); 1648932SBrad.Beckmann@amd.com } 16511266SBrad.Beckmann@amd.com int read_idx = idx + m_num_inst_only_ports + m_num_inst_data_ports; 1668932SBrad.Beckmann@amd.com return *readPorts[read_idx]; 1678922Swilliam.wang@arm.com } 16811266SBrad.Beckmann@amd.com // Note: currently the Ruby Tester does not support write only ports 16911266SBrad.Beckmann@amd.com // but that could easily be added here 1706899SN/A } 1716899SN/A} 1726899SN/A 1736899SN/Abool 1748975Sandreas.hansson@arm.comRubyTester::CpuPort::recvTimingResp(PacketPtr pkt) 1756899SN/A{ 1767053SN/A // retrieve the subblock and call hitCallback 1777053SN/A RubyTester::SenderState* senderState = 1787053SN/A safe_cast<RubyTester::SenderState*>(pkt->senderState); 1799542Sandreas.hansson@arm.com SubBlock& subblock = senderState->subBlock; 1806899SN/A 18111266SBrad.Beckmann@amd.com tester->hitCallback(globalIdx, &subblock); 1827053SN/A 1837053SN/A // Now that the tester has completed, delete the senderState 1847053SN/A // (includes sublock) and the packet, then return 1859542Sandreas.hansson@arm.com delete pkt->senderState; 1867053SN/A delete pkt->req; 1877053SN/A delete pkt; 1887053SN/A return true; 1896899SN/A} 1906899SN/A 1918950Sandreas.hansson@arm.combool 19211266SBrad.Beckmann@amd.comRubyTester::isInstOnlyCpuPort(int idx) 1938950Sandreas.hansson@arm.com{ 19411266SBrad.Beckmann@amd.com return idx < m_num_inst_only_ports; 19511266SBrad.Beckmann@amd.com} 19611266SBrad.Beckmann@amd.com 19711266SBrad.Beckmann@amd.combool 19811266SBrad.Beckmann@amd.comRubyTester::isInstDataCpuPort(int idx) 19911266SBrad.Beckmann@amd.com{ 20011266SBrad.Beckmann@amd.com return ((idx >= m_num_inst_only_ports) && 20111266SBrad.Beckmann@amd.com (idx < (m_num_inst_only_ports + m_num_inst_data_ports))); 2028950Sandreas.hansson@arm.com} 2038950Sandreas.hansson@arm.com 2048922Swilliam.wang@arm.comMasterPort* 2058932SBrad.Beckmann@amd.comRubyTester::getReadableCpuPort(int idx) 2066899SN/A{ 2078932SBrad.Beckmann@amd.com assert(idx >= 0 && idx < readPorts.size()); 2086899SN/A 2098932SBrad.Beckmann@amd.com return readPorts[idx]; 2108932SBrad.Beckmann@amd.com} 2118932SBrad.Beckmann@amd.com 2128932SBrad.Beckmann@amd.comMasterPort* 2138932SBrad.Beckmann@amd.comRubyTester::getWritableCpuPort(int idx) 2148932SBrad.Beckmann@amd.com{ 2158932SBrad.Beckmann@amd.com assert(idx >= 0 && idx < writePorts.size()); 2168932SBrad.Beckmann@amd.com 2178932SBrad.Beckmann@amd.com return writePorts[idx]; 2186899SN/A} 2196899SN/A 2207053SN/Avoid 2217053SN/ARubyTester::hitCallback(NodeID proc, SubBlock* data) 2226899SN/A{ 2237053SN/A // Mark that we made progress 2249475Snilay@cs.wisc.edu m_last_progress_vector[proc] = curCycle(); 2256899SN/A 22611266SBrad.Beckmann@amd.com DPRINTF(RubyTest, "completed request for proc: %d", proc); 22711266SBrad.Beckmann@amd.com DPRINTFR(RubyTest, " addr: 0x%x, size: %d, data: ", 2287053SN/A data->getAddress(), data->getSize()); 2297053SN/A for (int byte = 0; byte < data->getSize(); byte++) { 23011266SBrad.Beckmann@amd.com DPRINTFR(RubyTest, "%d ", data->getByte(byte)); 2317053SN/A } 23211266SBrad.Beckmann@amd.com DPRINTFR(RubyTest, "\n"); 2336899SN/A 2347053SN/A // This tells us our store has 'completed' or for a load gives us 2357053SN/A // back the data to make the check 2367053SN/A Check* check_ptr = m_checkTable_ptr->getCheck(data->getAddress()); 2377053SN/A assert(check_ptr != NULL); 2389475Snilay@cs.wisc.edu check_ptr->performCallback(proc, data, curCycle()); 2396899SN/A} 2406899SN/A 2417053SN/Avoid 2427053SN/ARubyTester::wakeup() 2437053SN/A{ 2447053SN/A if (m_checks_completed < m_checks_to_complete) { 2457053SN/A // Try to perform an action or check 2467053SN/A Check* check_ptr = m_checkTable_ptr->getRandomCheck(); 2477053SN/A assert(check_ptr != NULL); 2487053SN/A check_ptr->initiate(); 2497053SN/A 2507053SN/A checkForDeadlock(); 2517053SN/A 2527823Ssteve.reinhardt@amd.com schedule(checkStartEvent, curTick() + m_wakeup_frequency); 2537053SN/A } else { 2547053SN/A exitSimLoop("Ruby Tester completed"); 2557053SN/A } 2566899SN/A} 2576899SN/A 2587053SN/Avoid 2597053SN/ARubyTester::checkForDeadlock() 2606899SN/A{ 2617053SN/A int size = m_last_progress_vector.size(); 26210302Snilay@cs.wisc.edu Cycles current_time = curCycle(); 2637053SN/A for (int processor = 0; processor < size; processor++) { 2647053SN/A if ((current_time - m_last_progress_vector[processor]) > 2657053SN/A m_deadlock_threshold) { 2667805Snilay@cs.wisc.edu panic("Deadlock detected: current_time: %d last_progress_time: %d " 2677805Snilay@cs.wisc.edu "difference: %d processor: %d\n", 2687805Snilay@cs.wisc.edu current_time, m_last_progress_vector[processor], 2697805Snilay@cs.wisc.edu current_time - m_last_progress_vector[processor], processor); 2707053SN/A } 2716899SN/A } 2726899SN/A} 2736899SN/A 2747053SN/Avoid 2757055SN/ARubyTester::print(std::ostream& out) const 2766899SN/A{ 2777055SN/A out << "[RubyTester]" << std::endl; 2786899SN/A} 2796899SN/A 2806899SN/ARubyTester * 2816899SN/ARubyTesterParams::create() 2826899SN/A{ 2836899SN/A return new RubyTester(this); 2846899SN/A} 285