Check.cc revision 8190:8c68155aac00
12736Sktlim@umich.edu/* 22736Sktlim@umich.edu * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 32736Sktlim@umich.edu * Copyright (c) 2009 Advanced Micro Devices, Inc. 42736Sktlim@umich.edu * All rights reserved. 52736Sktlim@umich.edu * 62736Sktlim@umich.edu * Redistribution and use in source and binary forms, with or without 72736Sktlim@umich.edu * modification, are permitted provided that the following conditions are 82736Sktlim@umich.edu * met: redistributions of source code must retain the above copyright 92736Sktlim@umich.edu * notice, this list of conditions and the following disclaimer; 102736Sktlim@umich.edu * redistributions in binary form must reproduce the above copyright 112736Sktlim@umich.edu * notice, this list of conditions and the following disclaimer in the 122736Sktlim@umich.edu * documentation and/or other materials provided with the distribution; 132736Sktlim@umich.edu * neither the name of the copyright holders nor the names of its 142736Sktlim@umich.edu * contributors may be used to endorse or promote products derived from 152736Sktlim@umich.edu * this software without specific prior written permission. 162736Sktlim@umich.edu * 172736Sktlim@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182736Sktlim@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192736Sktlim@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202736Sktlim@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212736Sktlim@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222736Sktlim@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232736Sktlim@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242736Sktlim@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252736Sktlim@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262736Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272736Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282736Sktlim@umich.edu */ 292736Sktlim@umich.edu 302736Sktlim@umich.edu#include "cpu/testers/rubytest/Check.hh" 312736Sktlim@umich.edu#include "mem/ruby/common/SubBlock.hh" 322736Sktlim@umich.edu#include "mem/ruby/system/Sequencer.hh" 332736Sktlim@umich.edu#include "mem/ruby/system/System.hh" 342736Sktlim@umich.edu 352736Sktlim@umich.edutypedef RubyTester::SenderState SenderState; 362736Sktlim@umich.edu 372736Sktlim@umich.eduCheck::Check(const Address& address, const Address& pc, 382736Sktlim@umich.edu int _num_cpu_sequencers, RubyTester* _tester) 392736Sktlim@umich.edu : m_num_cpu_sequencers(_num_cpu_sequencers), m_tester_ptr(_tester) 402736Sktlim@umich.edu{ 412736Sktlim@umich.edu m_status = TesterStatus_Idle; 422736Sktlim@umich.edu 432736Sktlim@umich.edu pickValue(); 442736Sktlim@umich.edu pickInitiatingNode(); 452736Sktlim@umich.edu changeAddress(address); 462736Sktlim@umich.edu m_pc = pc; 472736Sktlim@umich.edu m_access_mode = RubyAccessMode(random() % RubyAccessMode_NUM); 482736Sktlim@umich.edu m_store_count = 0; 492736Sktlim@umich.edu} 502736Sktlim@umich.edu 512736Sktlim@umich.eduvoid 522736Sktlim@umich.eduCheck::initiate() 532736Sktlim@umich.edu{ 542736Sktlim@umich.edu DPRINTF(RubyTest, "initiating\n"); 552736Sktlim@umich.edu debugPrint(); 562736Sktlim@umich.edu 572736Sktlim@umich.edu // currently no protocols support prefetches 582736Sktlim@umich.edu if (false && (random() & 0xf) == 0) { 592736Sktlim@umich.edu initiatePrefetch(); // Prefetch from random processor 602736Sktlim@umich.edu } 612736Sktlim@umich.edu 622736Sktlim@umich.edu if (m_tester_ptr->getCheckFlush() && (random() & 0xff) == 0) { 632736Sktlim@umich.edu initiateFlush(); // issue a Flush request from random processor 642736Sktlim@umich.edu } 652736Sktlim@umich.edu 662736Sktlim@umich.edu if (m_status == TesterStatus_Idle) { 672736Sktlim@umich.edu initiateAction(); 682736Sktlim@umich.edu } else if (m_status == TesterStatus_Ready) { 692736Sktlim@umich.edu initiateCheck(); 702736Sktlim@umich.edu } else { 712736Sktlim@umich.edu // Pending - do nothing 722736Sktlim@umich.edu DPRINTF(RubyTest, 732736Sktlim@umich.edu "initiating action/check - failed: action/check is pending\n"); 742736Sktlim@umich.edu } 752736Sktlim@umich.edu} 762736Sktlim@umich.edu 772736Sktlim@umich.eduvoid 782736Sktlim@umich.eduCheck::initiatePrefetch() 792736Sktlim@umich.edu{ 802736Sktlim@umich.edu DPRINTF(RubyTest, "initiating prefetch\n"); 812736Sktlim@umich.edu 822736Sktlim@umich.edu int index = random() % m_num_cpu_sequencers; 832736Sktlim@umich.edu RubyTester::CpuPort* port = 842736Sktlim@umich.edu safe_cast<RubyTester::CpuPort*>(m_tester_ptr->getCpuPort(index)); 852736Sktlim@umich.edu 862736Sktlim@umich.edu Request::Flags flags; 872736Sktlim@umich.edu flags.set(Request::PREFETCH); 882736Sktlim@umich.edu 892736Sktlim@umich.edu Packet::Command cmd; 902736Sktlim@umich.edu 912736Sktlim@umich.edu // 1 in 8 chance this will be an exclusive prefetch 922736Sktlim@umich.edu if ((random() & 0x7) != 0) { 932736Sktlim@umich.edu cmd = MemCmd::ReadReq; 942736Sktlim@umich.edu 952736Sktlim@umich.edu // 50% chance that the request will be an instruction fetch 962736Sktlim@umich.edu if ((random() & 0x1) == 0) { 972736Sktlim@umich.edu flags.set(Request::INST_FETCH); 982736Sktlim@umich.edu } 992736Sktlim@umich.edu } else { 1002736Sktlim@umich.edu cmd = MemCmd::WriteReq; 1012736Sktlim@umich.edu flags.set(Request::PF_EXCLUSIVE); 1022736Sktlim@umich.edu } 1032736Sktlim@umich.edu 1042736Sktlim@umich.edu // Prefetches are assumed to be 0 sized 1052736Sktlim@umich.edu Request *req = new Request(m_address.getAddress(), 0, flags, curTick(), 1062736Sktlim@umich.edu m_pc.getAddress()); 1072736Sktlim@umich.edu req->setThreadContext(index, 0); 1082736Sktlim@umich.edu 1092736Sktlim@umich.edu PacketPtr pkt = new Packet(req, cmd, port->idx); 1102736Sktlim@umich.edu 1112736Sktlim@umich.edu // push the subblock onto the sender state. The sequencer will 1122736Sktlim@umich.edu // update the subblock on the return 1132736Sktlim@umich.edu pkt->senderState = 1142736Sktlim@umich.edu new SenderState(m_address, req->getSize(), pkt->senderState); 1152736Sktlim@umich.edu 1162736Sktlim@umich.edu if (port->sendTiming(pkt)) { 1172736Sktlim@umich.edu DPRINTF(RubyTest, "successfully initiated prefetch.\n"); 1184762Snate@binkert.org } else { 1194762Snate@binkert.org // If the packet did not issue, must delete 1202736Sktlim@umich.edu SenderState* senderState = safe_cast<SenderState*>(pkt->senderState); 1215034Smilesck@eecs.umich.edu pkt->senderState = senderState->saved; 1222736Sktlim@umich.edu delete senderState; 1232736Sktlim@umich.edu delete pkt->req; 1242736Sktlim@umich.edu delete pkt; 1252736Sktlim@umich.edu 1262736Sktlim@umich.edu DPRINTF(RubyTest, 1274762Snate@binkert.org "prefetch initiation failed because Port was busy.\n"); 1284762Snate@binkert.org } 1292736Sktlim@umich.edu} 1305034Smilesck@eecs.umich.edu 1312736Sktlim@umich.eduvoid 132Check::initiateFlush() 133{ 134 135 DPRINTF(RubyTest, "initiating Flush\n"); 136 137 int index = random() % m_num_cpu_sequencers; 138 RubyTester::CpuPort* port = 139 safe_cast<RubyTester::CpuPort*>(m_tester_ptr->getCpuPort(index)); 140 141 Request::Flags flags; 142 143 Request *req = new Request(m_address.getAddress(), CHECK_SIZE, flags, curTick(), 144 m_pc.getAddress()); 145 146 Packet::Command cmd; 147 148 cmd = MemCmd::FlushReq; 149 150 PacketPtr pkt = new Packet(req, cmd, port->idx); 151 152 // push the subblock onto the sender state. The sequencer will 153 // update the subblock on the return 154 pkt->senderState = 155 new SenderState(m_address, req->getSize(), pkt->senderState); 156 157 if (port->sendTiming(pkt)) { 158 DPRINTF(RubyTest, "initiating Flush - successful\n"); 159 } 160} 161 162void 163Check::initiateAction() 164{ 165 DPRINTF(RubyTest, "initiating Action\n"); 166 assert(m_status == TesterStatus_Idle); 167 168 int index = random() % m_num_cpu_sequencers; 169 RubyTester::CpuPort* port = 170 safe_cast<RubyTester::CpuPort*>(m_tester_ptr->getCpuPort(index)); 171 172 Request::Flags flags; 173 174 // Create the particular address for the next byte to be written 175 Address writeAddr(m_address.getAddress() + m_store_count); 176 177 // Stores are assumed to be 1 byte-sized 178 Request *req = new Request(writeAddr.getAddress(), 1, flags, curTick(), 179 m_pc.getAddress()); 180 181 req->setThreadContext(index, 0); 182 Packet::Command cmd; 183 184 // 1 out of 8 chance, issue an atomic rather than a write 185 // if ((random() & 0x7) == 0) { 186 // cmd = MemCmd::SwapReq; 187 // } else { 188 cmd = MemCmd::WriteReq; 189 // } 190 191 PacketPtr pkt = new Packet(req, cmd, port->idx); 192 uint8_t* writeData = new uint8_t; 193 *writeData = m_value + m_store_count; 194 pkt->dataDynamic(writeData); 195 196 DPRINTF(RubyTest, "data 0x%x check 0x%x\n", 197 *(pkt->getPtr<uint8_t>()), *writeData); 198 199 // push the subblock onto the sender state. The sequencer will 200 // update the subblock on the return 201 pkt->senderState = 202 new SenderState(writeAddr, req->getSize(), pkt->senderState); 203 204 if (port->sendTiming(pkt)) { 205 DPRINTF(RubyTest, "initiating action - successful\n"); 206 DPRINTF(RubyTest, "status before action update: %s\n", 207 (TesterStatus_to_string(m_status)).c_str()); 208 m_status = TesterStatus_Action_Pending; 209 } else { 210 // If the packet did not issue, must delete 211 // Note: No need to delete the data, the packet destructor 212 // will delete it 213 SenderState* senderState = safe_cast<SenderState*>(pkt->senderState); 214 pkt->senderState = senderState->saved; 215 delete senderState; 216 delete pkt->req; 217 delete pkt; 218 219 DPRINTF(RubyTest, "failed to initiate action - sequencer not ready\n"); 220 } 221 222 DPRINTF(RubyTest, "status after action update: %s\n", 223 (TesterStatus_to_string(m_status)).c_str()); 224} 225 226void 227Check::initiateCheck() 228{ 229 DPRINTF(RubyTest, "Initiating Check\n"); 230 assert(m_status == TesterStatus_Ready); 231 232 int index = random() % m_num_cpu_sequencers; 233 RubyTester::CpuPort* port = 234 safe_cast<RubyTester::CpuPort*>(m_tester_ptr->getCpuPort(index)); 235 236 Request::Flags flags; 237 238 // 50% chance that the request will be an instruction fetch 239 if ((random() & 0x1) == 0) { 240 flags.set(Request::INST_FETCH); 241 } 242 243 // Checks are sized depending on the number of bytes written 244 Request *req = new Request(m_address.getAddress(), CHECK_SIZE, flags, 245 curTick(), m_pc.getAddress()); 246 247 req->setThreadContext(index, 0); 248 PacketPtr pkt = new Packet(req, MemCmd::ReadReq, port->idx); 249 uint8_t* dataArray = new uint8_t[CHECK_SIZE]; 250 pkt->dataDynamicArray(dataArray); 251 252 // push the subblock onto the sender state. The sequencer will 253 // update the subblock on the return 254 pkt->senderState = 255 new SenderState(m_address, req->getSize(), pkt->senderState); 256 257 if (port->sendTiming(pkt)) { 258 DPRINTF(RubyTest, "initiating check - successful\n"); 259 DPRINTF(RubyTest, "status before check update: %s\n", 260 TesterStatus_to_string(m_status).c_str()); 261 m_status = TesterStatus_Check_Pending; 262 } else { 263 // If the packet did not issue, must delete 264 // Note: No need to delete the data, the packet destructor 265 // will delete it 266 SenderState* senderState = safe_cast<SenderState*>(pkt->senderState); 267 pkt->senderState = senderState->saved; 268 delete senderState; 269 delete pkt->req; 270 delete pkt; 271 272 DPRINTF(RubyTest, "failed to initiate check - cpu port not ready\n"); 273 } 274 275 DPRINTF(RubyTest, "status after check update: %s\n", 276 TesterStatus_to_string(m_status).c_str()); 277} 278 279void 280Check::performCallback(NodeID proc, SubBlock* data) 281{ 282 Address address = data->getAddress(); 283 284 // This isn't exactly right since we now have multi-byte checks 285 // assert(getAddress() == address); 286 287 assert(getAddress().getLineAddress() == address.getLineAddress()); 288 assert(data != NULL); 289 290 DPRINTF(RubyTest, "RubyTester Callback\n"); 291 debugPrint(); 292 293 if (m_status == TesterStatus_Action_Pending) { 294 DPRINTF(RubyTest, "Action callback write value: %d, currently %d\n", 295 (m_value + m_store_count), data->getByte(0)); 296 // Perform store one byte at a time 297 data->setByte(0, (m_value + m_store_count)); 298 m_store_count++; 299 if (m_store_count == CHECK_SIZE) { 300 m_status = TesterStatus_Ready; 301 } else { 302 m_status = TesterStatus_Idle; 303 } 304 DPRINTF(RubyTest, "Action callback return data now %d\n", 305 data->getByte(0)); 306 } else if (m_status == TesterStatus_Check_Pending) { 307 DPRINTF(RubyTest, "Check callback\n"); 308 // Perform load/check 309 for (int byte_number=0; byte_number<CHECK_SIZE; byte_number++) { 310 if (uint8(m_value + byte_number) != data->getByte(byte_number)) { 311 panic("Action/check failure: proc: %d address: %s data: %s " 312 "byte_number: %d m_value+byte_number: %d byte: %d %s" 313 "Time: %d\n", 314 proc, address, data, byte_number, 315 (int)m_value + byte_number, 316 (int)data->getByte(byte_number), *this, 317 g_eventQueue_ptr->getTime()); 318 } 319 } 320 DPRINTF(RubyTest, "Action/check success\n"); 321 debugPrint(); 322 323 // successful check complete, increment complete 324 m_tester_ptr->incrementCheckCompletions(); 325 326 m_status = TesterStatus_Idle; 327 pickValue(); 328 329 } else { 330 panic("Unexpected TesterStatus: %s proc: %d data: %s m_status: %s " 331 "time: %d\n", 332 *this, proc, data, m_status, g_eventQueue_ptr->getTime()); 333 } 334 335 DPRINTF(RubyTest, "proc: %d, Address: 0x%x\n", proc, 336 getAddress().getLineAddress()); 337 DPRINTF(RubyTest, "Callback done\n"); 338 debugPrint(); 339} 340 341void 342Check::changeAddress(const Address& address) 343{ 344 assert(m_status == TesterStatus_Idle || m_status == TesterStatus_Ready); 345 m_status = TesterStatus_Idle; 346 m_address = address; 347 m_store_count = 0; 348} 349 350void 351Check::pickValue() 352{ 353 assert(m_status == TesterStatus_Idle); 354 m_status = TesterStatus_Idle; 355 m_value = random() & 0xff; // One byte 356 m_store_count = 0; 357} 358 359void 360Check::pickInitiatingNode() 361{ 362 assert(m_status == TesterStatus_Idle || m_status == TesterStatus_Ready); 363 m_status = TesterStatus_Idle; 364 m_initiatingNode = (random() % m_num_cpu_sequencers); 365 DPRINTF(RubyTest, "picked initiating node %d\n", m_initiatingNode); 366 m_store_count = 0; 367} 368 369void 370Check::print(std::ostream& out) const 371{ 372 out << "[" 373 << m_address << ", value: " 374 << (int)m_value << ", status: " 375 << m_status << ", initiating node: " 376 << m_initiatingNode << ", store_count: " 377 << m_store_count 378 << "]" << std::flush; 379} 380 381void 382Check::debugPrint() 383{ 384 DPRINTF(RubyTest, 385 "[%#x, value: %d, status: %s, initiating node: %d, store_count: %d]\n", 386 m_address.getAddress(), (int)m_value, 387 TesterStatus_to_string(m_status).c_str(), 388 m_initiatingNode, m_store_count); 389} 390