memtest.hh revision 1634
12929Sktlim@umich.edu/* 22929Sktlim@umich.edu * Copyright (c) 2002-2004 The Regents of The University of Michigan 32932Sktlim@umich.edu * All rights reserved. 42929Sktlim@umich.edu * 52929Sktlim@umich.edu * Redistribution and use in source and binary forms, with or without 62929Sktlim@umich.edu * modification, are permitted provided that the following conditions are 72929Sktlim@umich.edu * met: redistributions of source code must retain the above copyright 82929Sktlim@umich.edu * notice, this list of conditions and the following disclaimer; 92929Sktlim@umich.edu * redistributions in binary form must reproduce the above copyright 102929Sktlim@umich.edu * notice, this list of conditions and the following disclaimer in the 112929Sktlim@umich.edu * documentation and/or other materials provided with the distribution; 122929Sktlim@umich.edu * neither the name of the copyright holders nor the names of its 132929Sktlim@umich.edu * contributors may be used to endorse or promote products derived from 142929Sktlim@umich.edu * this software without specific prior written permission. 152929Sktlim@umich.edu * 162929Sktlim@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172929Sktlim@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182929Sktlim@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192929Sktlim@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202929Sktlim@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212929Sktlim@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222929Sktlim@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232929Sktlim@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242929Sktlim@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252929Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262929Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272929Sktlim@umich.edu */ 282932Sktlim@umich.edu 292932Sktlim@umich.edu#ifndef __CPU_MEMTEST_MEMTEST_HH__ 302932Sktlim@umich.edu#define __CPU_MEMTEST_MEMTEST_HH__ 312929Sktlim@umich.edu 326007Ssteve.reinhardt@amd.com#include <set> 332929Sktlim@umich.edu 342929Sktlim@umich.edu#include "base/statistics.hh" 352929Sktlim@umich.edu#include "mem/functional_mem/functional_memory.hh" 362929Sktlim@umich.edu#include "mem/mem_interface.hh" 372929Sktlim@umich.edu#include "sim/eventq.hh" 382929Sktlim@umich.edu#include "sim/sim_exit.hh" 392929Sktlim@umich.edu#include "sim/sim_object.hh" 402929Sktlim@umich.edu#include "sim/stats.hh" 412929Sktlim@umich.edu 422929Sktlim@umich.educlass ExecContext; 432929Sktlim@umich.educlass MemTest : public SimObject 442929Sktlim@umich.edu{ 452929Sktlim@umich.edu public: 462929Sktlim@umich.edu 476007Ssteve.reinhardt@amd.com MemTest(const std::string &name, 486007Ssteve.reinhardt@amd.com MemInterface *_cache_interface, 496007Ssteve.reinhardt@amd.com FunctionalMemory *main_mem, 506007Ssteve.reinhardt@amd.com FunctionalMemory *check_mem, 516007Ssteve.reinhardt@amd.com unsigned _memorySize, 526007Ssteve.reinhardt@amd.com unsigned _percentReads, 536007Ssteve.reinhardt@amd.com unsigned _percentCopies, 546007Ssteve.reinhardt@amd.com unsigned _percentUncacheable, 556007Ssteve.reinhardt@amd.com unsigned _progressInterval, 566007Ssteve.reinhardt@amd.com unsigned _percentSourceUnaligned, 576007Ssteve.reinhardt@amd.com unsigned _percentDestUnaligned, 586007Ssteve.reinhardt@amd.com Addr _traceAddr, 596007Ssteve.reinhardt@amd.com Counter _max_loads); 606007Ssteve.reinhardt@amd.com 616007Ssteve.reinhardt@amd.com // register statistics 626007Ssteve.reinhardt@amd.com virtual void regStats(); 636007Ssteve.reinhardt@amd.com 646007Ssteve.reinhardt@amd.com inline Tick cycles(int numCycles) const { return numCycles; } 656007Ssteve.reinhardt@amd.com 666007Ssteve.reinhardt@amd.com // main simulation loop (one cycle) 676007Ssteve.reinhardt@amd.com void tick(); 686007Ssteve.reinhardt@amd.com 696007Ssteve.reinhardt@amd.com protected: 706007Ssteve.reinhardt@amd.com class TickEvent : public Event 716007Ssteve.reinhardt@amd.com { 726007Ssteve.reinhardt@amd.com private: 736007Ssteve.reinhardt@amd.com MemTest *cpu; 746007Ssteve.reinhardt@amd.com public: 756007Ssteve.reinhardt@amd.com TickEvent(MemTest *c) 762929Sktlim@umich.edu : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) {} 772929Sktlim@umich.edu void process() {cpu->tick();} 782929Sktlim@umich.edu virtual const char *description() { return "tick event"; } 796007Ssteve.reinhardt@amd.com }; 806007Ssteve.reinhardt@amd.com 816007Ssteve.reinhardt@amd.com TickEvent tickEvent; 826007Ssteve.reinhardt@amd.com 836007Ssteve.reinhardt@amd.com MemInterface *cacheInterface; 846007Ssteve.reinhardt@amd.com FunctionalMemory *mainMem; 852929Sktlim@umich.edu FunctionalMemory *checkMem; 862929Sktlim@umich.edu ExecContext *xc; 872929Sktlim@umich.edu 882929Sktlim@umich.edu unsigned size; // size of testing memory region 892929Sktlim@umich.edu 906011Ssteve.reinhardt@amd.com unsigned percentReads; // target percentage of read accesses 916007Ssteve.reinhardt@amd.com unsigned percentCopies; // target percentage of copy accesses 926007Ssteve.reinhardt@amd.com unsigned percentUncacheable; 936007Ssteve.reinhardt@amd.com 946007Ssteve.reinhardt@amd.com int id; 956007Ssteve.reinhardt@amd.com 966007Ssteve.reinhardt@amd.com std::set<unsigned> outstandingAddrs; 976007Ssteve.reinhardt@amd.com 986007Ssteve.reinhardt@amd.com unsigned blockSize; 996007Ssteve.reinhardt@amd.com 1006007Ssteve.reinhardt@amd.com Addr blockAddrMask; 1016007Ssteve.reinhardt@amd.com 1026007Ssteve.reinhardt@amd.com Addr blockAddr(Addr addr) 1036007Ssteve.reinhardt@amd.com { 1046007Ssteve.reinhardt@amd.com return (addr & ~blockAddrMask); 1056011Ssteve.reinhardt@amd.com } 1066007Ssteve.reinhardt@amd.com 1076007Ssteve.reinhardt@amd.com Addr traceBlockAddr; 1086007Ssteve.reinhardt@amd.com 1096007Ssteve.reinhardt@amd.com Addr baseAddr1; // fix this to option 1106007Ssteve.reinhardt@amd.com Addr baseAddr2; // fix this to option 1116007Ssteve.reinhardt@amd.com Addr uncacheAddr; 1126007Ssteve.reinhardt@amd.com 1136011Ssteve.reinhardt@amd.com unsigned progressInterval; // frequency of progress reports 1146007Ssteve.reinhardt@amd.com Tick nextProgressMessage; // access # for next progress report 1156007Ssteve.reinhardt@amd.com 1166007Ssteve.reinhardt@amd.com unsigned percentSourceUnaligned; 1176007Ssteve.reinhardt@amd.com unsigned percentDestUnaligned; 1186007Ssteve.reinhardt@amd.com 1196007Ssteve.reinhardt@amd.com Tick noResponseCycles; 1206007Ssteve.reinhardt@amd.com 1216011Ssteve.reinhardt@amd.com uint64_t numReads; 1226007Ssteve.reinhardt@amd.com uint64_t maxLoads; 1236007Ssteve.reinhardt@amd.com Stats::Scalar<> numReadsStat; 1246007Ssteve.reinhardt@amd.com Stats::Scalar<> numWritesStat; 1256007Ssteve.reinhardt@amd.com Stats::Scalar<> numCopiesStat; 1266007Ssteve.reinhardt@amd.com 1276008Ssteve.reinhardt@amd.com // called by MemCompleteEvent::process() 1286007Ssteve.reinhardt@amd.com void completeRequest(MemReqPtr &req, uint8_t *data); 1296008Ssteve.reinhardt@amd.com 1306008Ssteve.reinhardt@amd.com friend class MemCompleteEvent; 1316008Ssteve.reinhardt@amd.com}; 1326008Ssteve.reinhardt@amd.com 1336008Ssteve.reinhardt@amd.com 1346008Ssteve.reinhardt@amd.comclass MemCompleteEvent : public Event 1356008Ssteve.reinhardt@amd.com{ 1366007Ssteve.reinhardt@amd.com MemReqPtr req; 1376007Ssteve.reinhardt@amd.com uint8_t *data; 1386007Ssteve.reinhardt@amd.com MemTest *tester; 1396007Ssteve.reinhardt@amd.com 1406007Ssteve.reinhardt@amd.com public: 1412929Sktlim@umich.edu 1422929Sktlim@umich.edu MemCompleteEvent(MemReqPtr &_req, uint8_t *_data, MemTest *_tester) 1432929Sktlim@umich.edu : Event(&mainEventQueue), 1442929Sktlim@umich.edu req(_req), data(_data), tester(_tester) 1456007Ssteve.reinhardt@amd.com { 1466007Ssteve.reinhardt@amd.com } 1472929Sktlim@umich.edu 1482929Sktlim@umich.edu void process(); 1492929Sktlim@umich.edu 1502929Sktlim@umich.edu virtual const char *description(); 1516007Ssteve.reinhardt@amd.com}; 1526007Ssteve.reinhardt@amd.com 1532929Sktlim@umich.edu#endif // __CPU_MEMTEST_MEMTEST_HH__ 1542929Sktlim@umich.edu 1556007Ssteve.reinhardt@amd.com 1562929Sktlim@umich.edu 1572929Sktlim@umich.edu