memtest.hh revision 1400
111723Sar4jc@virginia.edu/* 211723Sar4jc@virginia.edu * Copyright (c) 2002-2004 The Regents of The University of Michigan 311723Sar4jc@virginia.edu * All rights reserved. 412120Sar4jc@virginia.edu * 511723Sar4jc@virginia.edu * Redistribution and use in source and binary forms, with or without 611723Sar4jc@virginia.edu * modification, are permitted provided that the following conditions are 711723Sar4jc@virginia.edu * met: redistributions of source code must retain the above copyright 811723Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer; 911723Sar4jc@virginia.edu * redistributions in binary form must reproduce the above copyright 1011723Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer in the 1111723Sar4jc@virginia.edu * documentation and/or other materials provided with the distribution; 1211723Sar4jc@virginia.edu * neither the name of the copyright holders nor the names of its 1311723Sar4jc@virginia.edu * contributors may be used to endorse or promote products derived from 1411723Sar4jc@virginia.edu * this software without specific prior written permission. 1511723Sar4jc@virginia.edu * 1611723Sar4jc@virginia.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711723Sar4jc@virginia.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1811723Sar4jc@virginia.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1911723Sar4jc@virginia.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2011723Sar4jc@virginia.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2111723Sar4jc@virginia.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2211723Sar4jc@virginia.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2311723Sar4jc@virginia.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2411723Sar4jc@virginia.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2511723Sar4jc@virginia.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2611723Sar4jc@virginia.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2711723Sar4jc@virginia.edu */ 2811723Sar4jc@virginia.edu 2911723Sar4jc@virginia.edu#ifndef __CPU_MEMTEST_MEMTEST_HH__ 3011723Sar4jc@virginia.edu#define __CPU_MEMTEST_MEMTEST_HH__ 3111723Sar4jc@virginia.edu 3211723Sar4jc@virginia.edu#include <set> 3311723Sar4jc@virginia.edu 3411723Sar4jc@virginia.edu#include "base/statistics.hh" 3511723Sar4jc@virginia.edu#include "mem/functional_mem/functional_memory.hh" 3611723Sar4jc@virginia.edu#include "mem/mem_interface.hh" 3712120Sar4jc@virginia.edu#include "sim/eventq.hh" 3812120Sar4jc@virginia.edu#include "sim/sim_exit.hh" 3912428Sar4jc@virginia.edu#include "sim/sim_object.hh" 4012120Sar4jc@virginia.edu#include "sim/stats.hh" 4112120Sar4jc@virginia.edu 4212120Sar4jc@virginia.educlass ExecContext; 4312120Sar4jc@virginia.educlass MemTest : public SimObject 4412120Sar4jc@virginia.edu{ 4512136Sar4jc@virginia.edu public: 4612849Sar4jc@virginia.edu 4712849Sar4jc@virginia.edu MemTest(const std::string &name, 4812120Sar4jc@virginia.edu MemInterface *_cache_interface, 4912428Sar4jc@virginia.edu FunctionalMemory *main_mem, 5012120Sar4jc@virginia.edu FunctionalMemory *check_mem, 5112120Sar4jc@virginia.edu unsigned _memorySize, 5212322Sar4jc@virginia.edu unsigned _percentReads, 5312120Sar4jc@virginia.edu unsigned _percentCopies, 5412120Sar4jc@virginia.edu unsigned _percentUncacheable, 5512120Sar4jc@virginia.edu unsigned _progressInterval, 5612322Sar4jc@virginia.edu unsigned _percentSourceUnaligned, 5711723Sar4jc@virginia.edu unsigned _percentDestUnaligned, 5812120Sar4jc@virginia.edu Addr _traceAddr, 5912322Sar4jc@virginia.edu Counter _max_loads); 6012322Sar4jc@virginia.edu 6112322Sar4jc@virginia.edu // register statistics 6212120Sar4jc@virginia.edu virtual void regStats(); 6312120Sar4jc@virginia.edu // main simulation loop (one cycle) 6412120Sar4jc@virginia.edu void tick(); 6512322Sar4jc@virginia.edu 6611723Sar4jc@virginia.edu protected: 6712120Sar4jc@virginia.edu class TickEvent : public Event 6812322Sar4jc@virginia.edu { 6912120Sar4jc@virginia.edu private: 7012120Sar4jc@virginia.edu MemTest *cpu; 7112120Sar4jc@virginia.edu public: 7212322Sar4jc@virginia.edu TickEvent(MemTest *c) 7311723Sar4jc@virginia.edu : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) {} 7412120Sar4jc@virginia.edu void process() {cpu->tick();} 7512120Sar4jc@virginia.edu virtual const char *description() { return "tick event"; } 7612120Sar4jc@virginia.edu }; 7712322Sar4jc@virginia.edu 7812120Sar4jc@virginia.edu TickEvent tickEvent; 7912120Sar4jc@virginia.edu 8012120Sar4jc@virginia.edu MemInterface *cacheInterface; 8112322Sar4jc@virginia.edu FunctionalMemory *mainMem; 8211723Sar4jc@virginia.edu FunctionalMemory *checkMem; 8312120Sar4jc@virginia.edu ExecContext *xc; 8412322Sar4jc@virginia.edu 8512322Sar4jc@virginia.edu unsigned size; // size of testing memory region 8612322Sar4jc@virginia.edu 8712120Sar4jc@virginia.edu unsigned percentReads; // target percentage of read accesses 8812120Sar4jc@virginia.edu unsigned percentCopies; // target percentage of copy accesses 8912120Sar4jc@virginia.edu unsigned percentUncacheable; 9012322Sar4jc@virginia.edu 9111723Sar4jc@virginia.edu int id; 9212120Sar4jc@virginia.edu 9312322Sar4jc@virginia.edu std::set<unsigned> outstandingAddrs; 9412120Sar4jc@virginia.edu 9512120Sar4jc@virginia.edu unsigned blockSize; 9612120Sar4jc@virginia.edu 9712322Sar4jc@virginia.edu Addr blockAddrMask; 9811723Sar4jc@virginia.edu 9911723Sar4jc@virginia.edu Addr blockAddr(Addr addr) 10011723Sar4jc@virginia.edu { 10112120Sar4jc@virginia.edu return (addr & ~blockAddrMask); 10212120Sar4jc@virginia.edu } 10312120Sar4jc@virginia.edu 10412120Sar4jc@virginia.edu Addr traceBlockAddr; 10512120Sar4jc@virginia.edu 10612120Sar4jc@virginia.edu Addr baseAddr1; // fix this to option 10712120Sar4jc@virginia.edu Addr baseAddr2; // fix this to option 10812136Sar4jc@virginia.edu Addr uncacheAddr; 10912136Sar4jc@virginia.edu 11012849Sar4jc@virginia.edu unsigned progressInterval; // frequency of progress reports 11112849Sar4jc@virginia.edu Tick nextProgressMessage; // access # for next progress report 11212136Sar4jc@virginia.edu 11312849Sar4jc@virginia.edu unsigned percentSourceUnaligned; 11412849Sar4jc@virginia.edu unsigned percentDestUnaligned; 11512136Sar4jc@virginia.edu 11612120Sar4jc@virginia.edu Tick noResponseCycles; 11712120Sar4jc@virginia.edu 11812120Sar4jc@virginia.edu uint64_t numReads; 11912120Sar4jc@virginia.edu uint64_t maxLoads; 12012120Sar4jc@virginia.edu Stats::Scalar<> numReadsStat; 12112120Sar4jc@virginia.edu Stats::Scalar<> numWritesStat; 12212120Sar4jc@virginia.edu Stats::Scalar<> numCopiesStat; 12312596Sqtt2@cornell.edu 12412849Sar4jc@virginia.edu // called by MemCompleteEvent::process() 12512849Sar4jc@virginia.edu void completeRequest(MemReqPtr &req, uint8_t *data); 12612596Sqtt2@cornell.edu 12712120Sar4jc@virginia.edu friend class MemCompleteEvent; 12812120Sar4jc@virginia.edu}; 12912120Sar4jc@virginia.edu 13012120Sar4jc@virginia.edu 13112120Sar4jc@virginia.educlass MemCompleteEvent : public Event 13212120Sar4jc@virginia.edu{ 13312120Sar4jc@virginia.edu MemReqPtr req; 13412596Sqtt2@cornell.edu uint8_t *data; 13512849Sar4jc@virginia.edu MemTest *tester; 13612849Sar4jc@virginia.edu 13712596Sqtt2@cornell.edu public: 13812120Sar4jc@virginia.edu 13912120Sar4jc@virginia.edu MemCompleteEvent(MemReqPtr &_req, uint8_t *_data, MemTest *_tester) 14012120Sar4jc@virginia.edu : Event(&mainEventQueue), 14112120Sar4jc@virginia.edu req(_req), data(_data), tester(_tester) 14212120Sar4jc@virginia.edu { 14312120Sar4jc@virginia.edu } 14412120Sar4jc@virginia.edu 14512120Sar4jc@virginia.edu void process(); 14612120Sar4jc@virginia.edu 14712120Sar4jc@virginia.edu virtual const char *description(); 14812120Sar4jc@virginia.edu}; 14912596Sqtt2@cornell.edu 15012849Sar4jc@virginia.edu#endif // __CPU_MEMTEST_MEMTEST_HH__ 15112849Sar4jc@virginia.edu 15212596Sqtt2@cornell.edu 15312120Sar4jc@virginia.edu 15412120Sar4jc@virginia.edu