memtest.hh revision 13784:1941dc118243
111527Sdavid.guillen@arm.com/* 211967Sandreas.sandberg@arm.com * Copyright (c) 2015 ARM Limited 311527Sdavid.guillen@arm.com * All rights reserved 411527Sdavid.guillen@arm.com * 511527Sdavid.guillen@arm.com * The license below extends only to copyright in the software and shall 611527Sdavid.guillen@arm.com * not be construed as granting a license to any other intellectual 711527Sdavid.guillen@arm.com * property including but not limited to intellectual property relating 811527Sdavid.guillen@arm.com * to a hardware implementation of the functionality of the software 911527Sdavid.guillen@arm.com * licensed hereunder. You may use the software subject to the license 1011527Sdavid.guillen@arm.com * terms below provided that you ensure that this notice is replicated 1111527Sdavid.guillen@arm.com * unmodified and in its entirety in all distributions of the software, 1211527Sdavid.guillen@arm.com * modified or unmodified, in source code or in binary form. 1311527Sdavid.guillen@arm.com * 1411527Sdavid.guillen@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1511527Sdavid.guillen@arm.com * All rights reserved. 1611527Sdavid.guillen@arm.com * 1711527Sdavid.guillen@arm.com * Redistribution and use in source and binary forms, with or without 1811527Sdavid.guillen@arm.com * modification, are permitted provided that the following conditions are 1911527Sdavid.guillen@arm.com * met: redistributions of source code must retain the above copyright 2011527Sdavid.guillen@arm.com * notice, this list of conditions and the following disclaimer; 2111527Sdavid.guillen@arm.com * redistributions in binary form must reproduce the above copyright 2211527Sdavid.guillen@arm.com * notice, this list of conditions and the following disclaimer in the 2311527Sdavid.guillen@arm.com * documentation and/or other materials provided with the distribution; 2411527Sdavid.guillen@arm.com * neither the name of the copyright holders nor the names of its 2511527Sdavid.guillen@arm.com * contributors may be used to endorse or promote products derived from 2611527Sdavid.guillen@arm.com * this software without specific prior written permission. 2711527Sdavid.guillen@arm.com * 2811527Sdavid.guillen@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2911527Sdavid.guillen@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3011527Sdavid.guillen@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3111527Sdavid.guillen@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3211527Sdavid.guillen@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3311527Sdavid.guillen@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3411527Sdavid.guillen@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3511527Sdavid.guillen@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3611527Sdavid.guillen@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3711527Sdavid.guillen@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3811527Sdavid.guillen@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3911527Sdavid.guillen@arm.com * 4011527Sdavid.guillen@arm.com * Authors: Erik Hallnor 4111527Sdavid.guillen@arm.com * Steve Reinhardt 4211527Sdavid.guillen@arm.com * Andreas Hansson 4311527Sdavid.guillen@arm.com */ 4411527Sdavid.guillen@arm.com 4511527Sdavid.guillen@arm.com#ifndef __CPU_MEMTEST_MEMTEST_HH__ 4611527Sdavid.guillen@arm.com#define __CPU_MEMTEST_MEMTEST_HH__ 4711527Sdavid.guillen@arm.com 4811527Sdavid.guillen@arm.com#include <set> 4911967Sandreas.sandberg@arm.com#include <unordered_map> 5011527Sdavid.guillen@arm.com 5111527Sdavid.guillen@arm.com#include "base/statistics.hh" 5211527Sdavid.guillen@arm.com#include "mem/mem_object.hh" 5311527Sdavid.guillen@arm.com#include "params/MemTest.hh" 5411527Sdavid.guillen@arm.com#include "sim/eventq.hh" 5511527Sdavid.guillen@arm.com#include "sim/stats.hh" 5611527Sdavid.guillen@arm.com 5711527Sdavid.guillen@arm.com/** 5811527Sdavid.guillen@arm.com * The MemTest class tests a cache coherent memory system by 5911527Sdavid.guillen@arm.com * generating false sharing and verifying the read data against a 6011527Sdavid.guillen@arm.com * reference updated on the completion of writes. Each tester reads 6111527Sdavid.guillen@arm.com * and writes a specific byte in a cache line, as determined by its 6211527Sdavid.guillen@arm.com * unique id. Thus, all requests issued by the MemTest instance are a 6311527Sdavid.guillen@arm.com * single byte and a specific address is only ever touched by a single 6411527Sdavid.guillen@arm.com * tester. 6511527Sdavid.guillen@arm.com * 6611527Sdavid.guillen@arm.com * In addition to verifying the data, the tester also has timeouts for 6711527Sdavid.guillen@arm.com * both requests and responses, thus checking that the memory-system 6811967Sandreas.sandberg@arm.com * is making progress. 6911967Sandreas.sandberg@arm.com */ 7011967Sandreas.sandberg@arm.comclass MemTest : public MemObject 7111967Sandreas.sandberg@arm.com{ 7211967Sandreas.sandberg@arm.com 7311967Sandreas.sandberg@arm.com public: 7411967Sandreas.sandberg@arm.com 7511967Sandreas.sandberg@arm.com typedef MemTestParams Params; 7611967Sandreas.sandberg@arm.com MemTest(const Params *p); 7711967Sandreas.sandberg@arm.com 7811967Sandreas.sandberg@arm.com virtual void regStats(); 7911967Sandreas.sandberg@arm.com 8011967Sandreas.sandberg@arm.com Port &getPort(const std::string &if_name, 8111967Sandreas.sandberg@arm.com PortID idx=InvalidPortID) override; 8211967Sandreas.sandberg@arm.com 8311967Sandreas.sandberg@arm.com protected: 8411527Sdavid.guillen@arm.com 8511527Sdavid.guillen@arm.com void tick(); 8611527Sdavid.guillen@arm.com 8711967Sandreas.sandberg@arm.com EventFunctionWrapper tickEvent; 8811967Sandreas.sandberg@arm.com 8911967Sandreas.sandberg@arm.com void noRequest(); 9011967Sandreas.sandberg@arm.com 9111967Sandreas.sandberg@arm.com EventFunctionWrapper noRequestEvent; 9211967Sandreas.sandberg@arm.com 9311967Sandreas.sandberg@arm.com void noResponse(); 9411967Sandreas.sandberg@arm.com 9511967Sandreas.sandberg@arm.com EventFunctionWrapper noResponseEvent; 9611967Sandreas.sandberg@arm.com 9711967Sandreas.sandberg@arm.com class CpuPort : public MasterPort 9811967Sandreas.sandberg@arm.com { 9911967Sandreas.sandberg@arm.com MemTest &memtest; 10011967Sandreas.sandberg@arm.com 10111967Sandreas.sandberg@arm.com public: 10211967Sandreas.sandberg@arm.com 10311967Sandreas.sandberg@arm.com CpuPort(const std::string &_name, MemTest &_memtest) 10411967Sandreas.sandberg@arm.com : MasterPort(_name, &_memtest), memtest(_memtest) 10511967Sandreas.sandberg@arm.com { } 10611967Sandreas.sandberg@arm.com 10711967Sandreas.sandberg@arm.com protected: 10811967Sandreas.sandberg@arm.com 10911967Sandreas.sandberg@arm.com bool recvTimingResp(PacketPtr pkt); 11011967Sandreas.sandberg@arm.com 11111967Sandreas.sandberg@arm.com void recvTimingSnoopReq(PacketPtr pkt) { } 11211967Sandreas.sandberg@arm.com 11311527Sdavid.guillen@arm.com void recvFunctionalSnoop(PacketPtr pkt) { } 11411527Sdavid.guillen@arm.com 11511527Sdavid.guillen@arm.com Tick recvAtomicSnoop(PacketPtr pkt) { return 0; } 11611527Sdavid.guillen@arm.com 11711527Sdavid.guillen@arm.com void recvReqRetry(); 11811968Sandreas.sandberg@arm.com }; 11911527Sdavid.guillen@arm.com 12011968Sandreas.sandberg@arm.com CpuPort port; 12111968Sandreas.sandberg@arm.com 12211968Sandreas.sandberg@arm.com PacketPtr retryPkt; 12311527Sdavid.guillen@arm.com 12411527Sdavid.guillen@arm.com const unsigned size; 12511967Sandreas.sandberg@arm.com 12611967Sandreas.sandberg@arm.com const Cycles interval; 12711967Sandreas.sandberg@arm.com 12811967Sandreas.sandberg@arm.com const unsigned percentReads; 12911967Sandreas.sandberg@arm.com const unsigned percentFunctional; 13011967Sandreas.sandberg@arm.com const unsigned percentUncacheable; 13111527Sdavid.guillen@arm.com 13211967Sandreas.sandberg@arm.com /** Request id for all generated traffic */ 13311967Sandreas.sandberg@arm.com MasterID masterId; 13411967Sandreas.sandberg@arm.com 13511527Sdavid.guillen@arm.com unsigned int id; 13611527Sdavid.guillen@arm.com 13711967Sandreas.sandberg@arm.com std::set<Addr> outstandingAddrs; 13811527Sdavid.guillen@arm.com 13911527Sdavid.guillen@arm.com // store the expected value for the addresses we have touched 14011527Sdavid.guillen@arm.com std::unordered_map<Addr, uint8_t> referenceData; 14111527Sdavid.guillen@arm.com 14211527Sdavid.guillen@arm.com const unsigned blockSize; 14311527Sdavid.guillen@arm.com 14411527Sdavid.guillen@arm.com const Addr blockAddrMask; 14511527Sdavid.guillen@arm.com 14611527Sdavid.guillen@arm.com /** 14711527Sdavid.guillen@arm.com * Get the block aligned address. 14811527Sdavid.guillen@arm.com * 14911527Sdavid.guillen@arm.com * @param addr Address to align 15011527Sdavid.guillen@arm.com * @return The block aligned address 15111527Sdavid.guillen@arm.com */ 15211527Sdavid.guillen@arm.com Addr blockAlign(Addr addr) const 15311527Sdavid.guillen@arm.com { 15411527Sdavid.guillen@arm.com return (addr & ~blockAddrMask); 155 } 156 157 Addr baseAddr1; 158 Addr baseAddr2; 159 Addr uncacheAddr; 160 161 const unsigned progressInterval; // frequency of progress reports 162 const Cycles progressCheck; 163 Tick nextProgressMessage; // access # for next progress report 164 165 uint64_t numReads; 166 uint64_t numWrites; 167 const uint64_t maxLoads; 168 169 const bool atomic; 170 171 const bool suppressFuncWarnings; 172 173 Stats::Scalar numReadsStat; 174 Stats::Scalar numWritesStat; 175 176 /** 177 * Complete a request by checking the response. 178 * 179 * @param pkt Response packet 180 * @param functional Whether the access was functional or not 181 */ 182 void completeRequest(PacketPtr pkt, bool functional = false); 183 184 bool sendPkt(PacketPtr pkt); 185 186 void recvRetry(); 187 188}; 189 190#endif // __CPU_MEMTEST_MEMTEST_HH__ 191