memtest.cc revision 9301:1e8d01c15a77
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Erik Hallnor 29 * Steve Reinhardt 30 */ 31 32// FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded 33 34#include <iomanip> 35#include <set> 36#include <string> 37#include <vector> 38 39#include "base/misc.hh" 40#include "base/statistics.hh" 41#include "cpu/testers/memtest/memtest.hh" 42#include "debug/MemTest.hh" 43#include "mem/mem_object.hh" 44#include "mem/packet.hh" 45#include "mem/port.hh" 46#include "mem/request.hh" 47#include "sim/sim_events.hh" 48#include "sim/stats.hh" 49#include "sim/system.hh" 50 51using namespace std; 52 53int TESTER_ALLOCATOR=0; 54 55bool 56MemTest::CpuPort::recvTimingResp(PacketPtr pkt) 57{ 58 memtest->completeRequest(pkt); 59 return true; 60} 61 62void 63MemTest::CpuPort::recvRetry() 64{ 65 memtest->doRetry(); 66} 67 68void 69MemTest::sendPkt(PacketPtr pkt) { 70 if (atomic) { 71 cachePort.sendAtomic(pkt); 72 completeRequest(pkt); 73 } 74 else if (!cachePort.sendTimingReq(pkt)) { 75 DPRINTF(MemTest, "accessRetry setting to true\n"); 76 77 // 78 // dma requests should never be retried 79 // 80 if (issueDmas) { 81 panic("Nacked DMA requests are not supported\n"); 82 } 83 accessRetry = true; 84 retryPkt = pkt; 85 } else { 86 if (issueDmas) { 87 dmaOutstanding = true; 88 } 89 } 90 91} 92 93MemTest::MemTest(const Params *p) 94 : MemObject(p), 95 tickEvent(this), 96 cachePort("test", this), 97 funcPort("functional", this), 98 funcProxy(funcPort), 99 retryPkt(NULL), 100// mainMem(main_mem), 101// checkMem(check_mem), 102 size(p->memory_size), 103 percentReads(p->percent_reads), 104 percentFunctional(p->percent_functional), 105 percentUncacheable(p->percent_uncacheable), 106 issueDmas(p->issue_dmas), 107 masterId(p->sys->getMasterId(name())), 108 progressInterval(p->progress_interval), 109 nextProgressMessage(p->progress_interval), 110 percentSourceUnaligned(p->percent_source_unaligned), 111 percentDestUnaligned(p->percent_dest_unaligned), 112 maxLoads(p->max_loads), 113 atomic(p->atomic), 114 suppress_func_warnings(p->suppress_func_warnings) 115{ 116 id = TESTER_ALLOCATOR++; 117 118 // Needs to be masked off once we know the block size. 119 traceBlockAddr = p->trace_addr; 120 baseAddr1 = 0x100000; 121 baseAddr2 = 0x400000; 122 uncacheAddr = 0x800000; 123 124 // set up counters 125 noResponseCycles = 0; 126 numReads = 0; 127 numWrites = 0; 128 schedule(tickEvent, 0); 129 130 accessRetry = false; 131 dmaOutstanding = false; 132} 133 134BaseMasterPort & 135MemTest::getMasterPort(const std::string &if_name, PortID idx) 136{ 137 if (if_name == "functional") 138 return funcPort; 139 else if (if_name == "test") 140 return cachePort; 141 else 142 return MemObject::getMasterPort(if_name, idx); 143} 144 145void 146MemTest::init() 147{ 148 // By the time init() is called, the ports should be hooked up. 149 blockSize = cachePort.peerBlockSize(); 150 blockAddrMask = blockSize - 1; 151 traceBlockAddr = blockAddr(traceBlockAddr); 152 153 // initial memory contents for both physical memory and functional 154 // memory should be 0; no need to initialize them. 155} 156 157 158void 159MemTest::completeRequest(PacketPtr pkt) 160{ 161 Request *req = pkt->req; 162 163 if (issueDmas) { 164 dmaOutstanding = false; 165 } 166 167 DPRINTF(MemTest, "completing %s at address %x (blk %x) %s\n", 168 pkt->isWrite() ? "write" : "read", 169 req->getPaddr(), blockAddr(req->getPaddr()), 170 pkt->isError() ? "error" : "success"); 171 172 MemTestSenderState *state = 173 dynamic_cast<MemTestSenderState *>(pkt->senderState); 174 175 uint8_t *data = state->data; 176 uint8_t *pkt_data = pkt->getPtr<uint8_t>(); 177 178 //Remove the address from the list of outstanding 179 std::set<unsigned>::iterator removeAddr = 180 outstandingAddrs.find(req->getPaddr()); 181 assert(removeAddr != outstandingAddrs.end()); 182 outstandingAddrs.erase(removeAddr); 183 184 if (pkt->isError()) { 185 if (!suppress_func_warnings) { 186 warn("Functional %s access failed at %#x\n", 187 pkt->isWrite() ? "write" : "read", req->getPaddr()); 188 } 189 } else { 190 if (pkt->isRead()) { 191 if (memcmp(pkt_data, data, pkt->getSize()) != 0) { 192 panic("%s: read of %x (blk %x) @ cycle %d " 193 "returns %x, expected %x\n", name(), 194 req->getPaddr(), blockAddr(req->getPaddr()), curTick(), 195 *pkt_data, *data); 196 } 197 198 numReads++; 199 numReadsStat++; 200 201 if (numReads == (uint64_t)nextProgressMessage) { 202 ccprintf(cerr, "%s: completed %d read, %d write accesses @%d\n", 203 name(), numReads, numWrites, curTick()); 204 nextProgressMessage += progressInterval; 205 } 206 207 if (maxLoads != 0 && numReads >= maxLoads) 208 exitSimLoop("maximum number of loads reached"); 209 } else { 210 assert(pkt->isWrite()); 211 funcProxy.writeBlob(req->getPaddr(), pkt_data, req->getSize()); 212 numWrites++; 213 numWritesStat++; 214 } 215 } 216 217 noResponseCycles = 0; 218 delete state; 219 delete [] data; 220 delete pkt->req; 221 delete pkt; 222} 223 224void 225MemTest::regStats() 226{ 227 using namespace Stats; 228 229 numReadsStat 230 .name(name() + ".num_reads") 231 .desc("number of read accesses completed") 232 ; 233 234 numWritesStat 235 .name(name() + ".num_writes") 236 .desc("number of write accesses completed") 237 ; 238 239 numCopiesStat 240 .name(name() + ".num_copies") 241 .desc("number of copy accesses completed") 242 ; 243} 244 245void 246MemTest::tick() 247{ 248 if (!tickEvent.scheduled()) 249 schedule(tickEvent, clockEdge(Cycles(1))); 250 251 if (++noResponseCycles >= 500000) { 252 if (issueDmas) { 253 cerr << "DMA tester "; 254 } 255 cerr << name() << ": deadlocked at cycle " << curTick() << endl; 256 fatal(""); 257 } 258 259 if (accessRetry || (issueDmas && dmaOutstanding)) { 260 DPRINTF(MemTest, "MemTester waiting on accessRetry or DMA response\n"); 261 return; 262 } 263 264 //make new request 265 unsigned cmd = random() % 100; 266 unsigned offset = random() % size; 267 unsigned base = random() % 2; 268 uint64_t data = random(); 269 unsigned access_size = random() % 4; 270 bool uncacheable = (random() % 100) < percentUncacheable; 271 272 unsigned dma_access_size = random() % 4; 273 274 //If we aren't doing copies, use id as offset, and do a false sharing 275 //mem tester 276 //We can eliminate the lower bits of the offset, and then use the id 277 //to offset within the blks 278 offset = blockAddr(offset); 279 offset += id; 280 access_size = 0; 281 dma_access_size = 0; 282 283 Request::Flags flags; 284 Addr paddr; 285 286 if (uncacheable) { 287 flags.set(Request::UNCACHEABLE); 288 paddr = uncacheAddr + offset; 289 } else { 290 paddr = ((base) ? baseAddr1 : baseAddr2) + offset; 291 } 292 293 // For now we only allow one outstanding request per address 294 // per tester This means we assume CPU does write forwarding 295 // to reads that alias something in the cpu store buffer. 296 if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) { 297 return; 298 } 299 300 bool do_functional = (random() % 100 < percentFunctional) && !uncacheable; 301 Request *req = new Request(); 302 uint8_t *result = new uint8_t[8]; 303 304 if (issueDmas) { 305 paddr &= ~((1 << dma_access_size) - 1); 306 req->setPhys(paddr, 1 << dma_access_size, flags, masterId); 307 req->setThreadContext(id,0); 308 } else { 309 paddr &= ~((1 << access_size) - 1); 310 req->setPhys(paddr, 1 << access_size, flags, masterId); 311 req->setThreadContext(id,0); 312 } 313 assert(req->getSize() == 1); 314 315 if (cmd < percentReads) { 316 // read 317 outstandingAddrs.insert(paddr); 318 319 // ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin 320 funcProxy.readBlob(req->getPaddr(), result, req->getSize()); 321 322 DPRINTF(MemTest, 323 "id %d initiating %sread at addr %x (blk %x) expecting %x\n", 324 id, do_functional ? "functional " : "", req->getPaddr(), 325 blockAddr(req->getPaddr()), *result); 326 327 PacketPtr pkt = new Packet(req, MemCmd::ReadReq); 328 pkt->dataDynamicArray(new uint8_t[req->getSize()]); 329 MemTestSenderState *state = new MemTestSenderState(result); 330 pkt->senderState = state; 331 332 if (do_functional) { 333 assert(pkt->needsResponse()); 334 pkt->setSuppressFuncError(); 335 cachePort.sendFunctional(pkt); 336 completeRequest(pkt); 337 } else { 338 sendPkt(pkt); 339 } 340 } else { 341 // write 342 outstandingAddrs.insert(paddr); 343 344 DPRINTF(MemTest, "initiating %swrite at addr %x (blk %x) value %x\n", 345 do_functional ? "functional " : "", req->getPaddr(), 346 blockAddr(req->getPaddr()), data & 0xff); 347 348 PacketPtr pkt = new Packet(req, MemCmd::WriteReq); 349 uint8_t *pkt_data = new uint8_t[req->getSize()]; 350 pkt->dataDynamicArray(pkt_data); 351 memcpy(pkt_data, &data, req->getSize()); 352 MemTestSenderState *state = new MemTestSenderState(result); 353 pkt->senderState = state; 354 355 if (do_functional) { 356 pkt->setSuppressFuncError(); 357 cachePort.sendFunctional(pkt); 358 completeRequest(pkt); 359 } else { 360 sendPkt(pkt); 361 } 362 } 363} 364 365void 366MemTest::doRetry() 367{ 368 if (cachePort.sendTimingReq(retryPkt)) { 369 DPRINTF(MemTest, "accessRetry setting to false\n"); 370 accessRetry = false; 371 retryPkt = NULL; 372 } 373} 374 375 376void 377MemTest::printAddr(Addr a) 378{ 379 cachePort.printAddr(a); 380} 381 382 383MemTest * 384MemTestParams::create() 385{ 386 return new MemTest(this); 387} 388