memtest.cc revision 8436:5648986156db 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 *          Steve Reinhardt
30 */
31
32// FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded
33
34#include <iomanip>
35#include <set>
36#include <string>
37#include <vector>
38
39#include "base/misc.hh"
40#include "base/statistics.hh"
41#include "cpu/testers/memtest/memtest.hh"
42#include "debug/MemTest.hh"
43#include "mem/mem_object.hh"
44#include "mem/packet.hh"
45#include "mem/port.hh"
46#include "mem/request.hh"
47#include "sim/sim_events.hh"
48#include "sim/stats.hh"
49
50using namespace std;
51
52int TESTER_ALLOCATOR=0;
53
54bool
55MemTest::CpuPort::recvTiming(PacketPtr pkt)
56{
57    if (pkt->isResponse()) {
58        memtest->completeRequest(pkt);
59    } else {
60        // must be snoop upcall
61        assert(pkt->isRequest());
62        assert(pkt->getDest() == Packet::Broadcast);
63    }
64    return true;
65}
66
67Tick
68MemTest::CpuPort::recvAtomic(PacketPtr pkt)
69{
70    // must be snoop upcall
71    assert(pkt->isRequest());
72    assert(pkt->getDest() == Packet::Broadcast);
73    return curTick();
74}
75
76void
77MemTest::CpuPort::recvFunctional(PacketPtr pkt)
78{
79    //Do nothing if we see one come through
80//    if (curTick() != 0)//Supress warning durring initialization
81//        warn("Functional Writes not implemented in MemTester\n");
82    //Need to find any response values that intersect and update
83    return;
84}
85
86void
87MemTest::CpuPort::recvStatusChange(Status status)
88{
89    if (status == RangeChange) {
90        if (!snoopRangeSent) {
91            snoopRangeSent = true;
92            sendStatusChange(Port::RangeChange);
93        }
94        return;
95    }
96
97    panic("MemTest doesn't expect recvStatusChange callback!");
98}
99
100void
101MemTest::CpuPort::recvRetry()
102{
103    memtest->doRetry();
104}
105
106void
107MemTest::sendPkt(PacketPtr pkt) {
108    if (atomic) {
109        cachePort.sendAtomic(pkt);
110        completeRequest(pkt);
111    }
112    else if (!cachePort.sendTiming(pkt)) {
113        DPRINTF(MemTest, "accessRetry setting to true\n");
114
115        //
116        // dma requests should never be retried
117        //
118        if (issueDmas) {
119            panic("Nacked DMA requests are not supported\n");
120        }
121        accessRetry = true;
122        retryPkt = pkt;
123    } else {
124        if (issueDmas) {
125            dmaOutstanding = true;
126        }
127    }
128
129}
130
131MemTest::MemTest(const Params *p)
132    : MemObject(p),
133      tickEvent(this),
134      cachePort("test", this),
135      funcPort("functional", this),
136      retryPkt(NULL),
137//      mainMem(main_mem),
138//      checkMem(check_mem),
139      size(p->memory_size),
140      percentReads(p->percent_reads),
141      percentFunctional(p->percent_functional),
142      percentUncacheable(p->percent_uncacheable),
143      issueDmas(p->issue_dmas),
144      progressInterval(p->progress_interval),
145      nextProgressMessage(p->progress_interval),
146      percentSourceUnaligned(p->percent_source_unaligned),
147      percentDestUnaligned(p->percent_dest_unaligned),
148      maxLoads(p->max_loads),
149      atomic(p->atomic),
150      suppress_func_warnings(p->suppress_func_warnings)
151{
152    cachePort.snoopRangeSent = false;
153    funcPort.snoopRangeSent = true;
154
155    id = TESTER_ALLOCATOR++;
156
157    // Needs to be masked off once we know the block size.
158    traceBlockAddr = p->trace_addr;
159    baseAddr1 = 0x100000;
160    baseAddr2 = 0x400000;
161    uncacheAddr = 0x800000;
162
163    // set up counters
164    noResponseCycles = 0;
165    numReads = 0;
166    numWrites = 0;
167    schedule(tickEvent, 0);
168
169    accessRetry = false;
170    dmaOutstanding = false;
171}
172
173Port *
174MemTest::getPort(const std::string &if_name, int idx)
175{
176    if (if_name == "functional")
177        return &funcPort;
178    else if (if_name == "test")
179        return &cachePort;
180    else
181        panic("No Such Port\n");
182}
183
184void
185MemTest::init()
186{
187    // By the time init() is called, the ports should be hooked up.
188    blockSize = cachePort.peerBlockSize();
189    blockAddrMask = blockSize - 1;
190    traceBlockAddr = blockAddr(traceBlockAddr);
191
192    // initial memory contents for both physical memory and functional
193    // memory should be 0; no need to initialize them.
194}
195
196
197void
198MemTest::completeRequest(PacketPtr pkt)
199{
200    Request *req = pkt->req;
201
202    if (issueDmas) {
203        dmaOutstanding = false;
204    }
205
206    DPRINTF(MemTest, "completing %s at address %x (blk %x) %s\n",
207            pkt->isWrite() ? "write" : "read",
208            req->getPaddr(), blockAddr(req->getPaddr()),
209            pkt->isError() ? "error" : "success");
210
211    MemTestSenderState *state =
212        dynamic_cast<MemTestSenderState *>(pkt->senderState);
213
214    uint8_t *data = state->data;
215    uint8_t *pkt_data = pkt->getPtr<uint8_t>();
216
217    //Remove the address from the list of outstanding
218    std::set<unsigned>::iterator removeAddr =
219        outstandingAddrs.find(req->getPaddr());
220    assert(removeAddr != outstandingAddrs.end());
221    outstandingAddrs.erase(removeAddr);
222
223    if (pkt->isError()) {
224        if (!suppress_func_warnings) {
225          warn("Functional Access failed for %x at %x\n",
226               pkt->isWrite() ? "write" : "read", req->getPaddr());
227        }
228    } else {
229        if (pkt->isRead()) {
230            if (memcmp(pkt_data, data, pkt->getSize()) != 0) {
231                panic("%s: read of %x (blk %x) @ cycle %d "
232                      "returns %x, expected %x\n", name(),
233                      req->getPaddr(), blockAddr(req->getPaddr()), curTick(),
234                      *pkt_data, *data);
235            }
236
237            numReads++;
238            numReadsStat++;
239
240            if (numReads == (uint64_t)nextProgressMessage) {
241                ccprintf(cerr, "%s: completed %d read, %d write accesses @%d\n",
242                         name(), numReads, numWrites, curTick());
243                nextProgressMessage += progressInterval;
244            }
245
246            if (maxLoads != 0 && numReads >= maxLoads)
247                exitSimLoop("maximum number of loads reached");
248        } else {
249            assert(pkt->isWrite());
250            funcPort.writeBlob(req->getPaddr(), pkt_data, req->getSize());
251            numWrites++;
252            numWritesStat++;
253        }
254    }
255
256    noResponseCycles = 0;
257    delete state;
258    delete [] data;
259    delete pkt->req;
260    delete pkt;
261}
262
263void
264MemTest::regStats()
265{
266    using namespace Stats;
267
268    numReadsStat
269        .name(name() + ".num_reads")
270        .desc("number of read accesses completed")
271        ;
272
273    numWritesStat
274        .name(name() + ".num_writes")
275        .desc("number of write accesses completed")
276        ;
277
278    numCopiesStat
279        .name(name() + ".num_copies")
280        .desc("number of copy accesses completed")
281        ;
282}
283
284void
285MemTest::tick()
286{
287    if (!tickEvent.scheduled())
288        schedule(tickEvent, curTick() + ticks(1));
289
290    if (++noResponseCycles >= 500000) {
291        if (issueDmas) {
292            cerr << "DMA tester ";
293        }
294        cerr << name() << ": deadlocked at cycle " << curTick() << endl;
295        fatal("");
296    }
297
298    if (accessRetry || (issueDmas && dmaOutstanding)) {
299        DPRINTF(MemTest, "MemTester waiting on accessRetry or DMA response\n");
300        return;
301    }
302
303    //make new request
304    unsigned cmd = random() % 100;
305    unsigned offset = random() % size;
306    unsigned base = random() % 2;
307    uint64_t data = random();
308    unsigned access_size = random() % 4;
309    bool uncacheable = (random() % 100) < percentUncacheable;
310
311    unsigned dma_access_size = random() % 4;
312
313    //If we aren't doing copies, use id as offset, and do a false sharing
314    //mem tester
315    //We can eliminate the lower bits of the offset, and then use the id
316    //to offset within the blks
317    offset = blockAddr(offset);
318    offset += id;
319    access_size = 0;
320    dma_access_size = 0;
321
322    Request *req = new Request();
323    Request::Flags flags;
324    Addr paddr;
325
326    if (uncacheable) {
327        flags.set(Request::UNCACHEABLE);
328        paddr = uncacheAddr + offset;
329    } else  {
330        paddr = ((base) ? baseAddr1 : baseAddr2) + offset;
331    }
332    bool do_functional = (random() % 100 < percentFunctional) && !uncacheable;
333
334    if (issueDmas) {
335        paddr &= ~((1 << dma_access_size) - 1);
336        req->setPhys(paddr, 1 << dma_access_size, flags);
337        req->setThreadContext(id,0);
338    } else {
339        paddr &= ~((1 << access_size) - 1);
340        req->setPhys(paddr, 1 << access_size, flags);
341        req->setThreadContext(id,0);
342    }
343    assert(req->getSize() == 1);
344
345    uint8_t *result = new uint8_t[8];
346
347    if (cmd < percentReads) {
348        // read
349
350        // For now we only allow one outstanding request per address
351        // per tester This means we assume CPU does write forwarding
352        // to reads that alias something in the cpu store buffer.
353        if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) {
354            delete [] result;
355            delete req;
356            return;
357        }
358
359        outstandingAddrs.insert(paddr);
360
361        // ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin
362        funcPort.readBlob(req->getPaddr(), result, req->getSize());
363
364        DPRINTF(MemTest,
365                "id %d initiating %sread at addr %x (blk %x) expecting %x\n",
366                id, do_functional ? "functional " : "", req->getPaddr(),
367                blockAddr(req->getPaddr()), *result);
368
369        PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
370        pkt->setSrc(0);
371        pkt->dataDynamicArray(new uint8_t[req->getSize()]);
372        MemTestSenderState *state = new MemTestSenderState(result);
373        pkt->senderState = state;
374
375        if (do_functional) {
376            assert(pkt->needsResponse());
377            pkt->setSuppressFuncError();
378            cachePort.sendFunctional(pkt);
379            completeRequest(pkt);
380        } else {
381            sendPkt(pkt);
382        }
383    } else {
384        // write
385
386        // For now we only allow one outstanding request per addreess
387        // per tester.  This means we assume CPU does write forwarding
388        // to reads that alias something in the cpu store buffer.
389        if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) {
390            delete [] result;
391            delete req;
392            return;
393        }
394
395        outstandingAddrs.insert(paddr);
396
397        DPRINTF(MemTest, "initiating %swrite at addr %x (blk %x) value %x\n",
398                do_functional ? "functional " : "", req->getPaddr(),
399                blockAddr(req->getPaddr()), data & 0xff);
400
401        PacketPtr pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast);
402        pkt->setSrc(0);
403        uint8_t *pkt_data = new uint8_t[req->getSize()];
404        pkt->dataDynamicArray(pkt_data);
405        memcpy(pkt_data, &data, req->getSize());
406        MemTestSenderState *state = new MemTestSenderState(result);
407        pkt->senderState = state;
408
409        if (do_functional) {
410            pkt->setSuppressFuncError();
411            cachePort.sendFunctional(pkt);
412            completeRequest(pkt);
413        } else {
414            sendPkt(pkt);
415        }
416    }
417}
418
419void
420MemTest::doRetry()
421{
422    if (cachePort.sendTiming(retryPkt)) {
423        DPRINTF(MemTest, "accessRetry setting to false\n");
424        accessRetry = false;
425        retryPkt = NULL;
426    }
427}
428
429
430void
431MemTest::printAddr(Addr a)
432{
433    cachePort.printAddr(a);
434}
435
436
437MemTest *
438MemTestParams::create()
439{
440    return new MemTest(this);
441}
442