memtest.cc revision 7657:4552d30af57f 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 *          Steve Reinhardt
30 */
31
32// FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded
33
34#include <iomanip>
35#include <set>
36#include <string>
37#include <vector>
38
39#include "base/misc.hh"
40#include "base/statistics.hh"
41#include "cpu/testers/memtest/memtest.hh"
42#include "mem/mem_object.hh"
43#include "mem/port.hh"
44#include "mem/packet.hh"
45#include "mem/request.hh"
46#include "sim/sim_events.hh"
47#include "sim/stats.hh"
48
49using namespace std;
50
51int TESTER_ALLOCATOR=0;
52
53bool
54MemTest::CpuPort::recvTiming(PacketPtr pkt)
55{
56    if (pkt->isResponse()) {
57        memtest->completeRequest(pkt);
58    } else {
59        // must be snoop upcall
60        assert(pkt->isRequest());
61        assert(pkt->getDest() == Packet::Broadcast);
62    }
63    return true;
64}
65
66Tick
67MemTest::CpuPort::recvAtomic(PacketPtr pkt)
68{
69    // must be snoop upcall
70    assert(pkt->isRequest());
71    assert(pkt->getDest() == Packet::Broadcast);
72    return curTick;
73}
74
75void
76MemTest::CpuPort::recvFunctional(PacketPtr pkt)
77{
78    //Do nothing if we see one come through
79//    if (curTick != 0)//Supress warning durring initialization
80//        warn("Functional Writes not implemented in MemTester\n");
81    //Need to find any response values that intersect and update
82    return;
83}
84
85void
86MemTest::CpuPort::recvStatusChange(Status status)
87{
88    if (status == RangeChange) {
89        if (!snoopRangeSent) {
90            snoopRangeSent = true;
91            sendStatusChange(Port::RangeChange);
92        }
93        return;
94    }
95
96    panic("MemTest doesn't expect recvStatusChange callback!");
97}
98
99void
100MemTest::CpuPort::recvRetry()
101{
102    memtest->doRetry();
103}
104
105void
106MemTest::sendPkt(PacketPtr pkt) {
107    if (atomic) {
108        cachePort.sendAtomic(pkt);
109        completeRequest(pkt);
110    }
111    else if (!cachePort.sendTiming(pkt)) {
112        DPRINTF(MemTest, "accessRetry setting to true\n");
113
114        //
115        // dma requests should never be retried
116        //
117        if (issueDmas) {
118            panic("Nacked DMA requests are not supported\n");
119        }
120        accessRetry = true;
121        retryPkt = pkt;
122    } else {
123        if (issueDmas) {
124            dmaOutstanding = true;
125        }
126    }
127
128}
129
130MemTest::MemTest(const Params *p)
131    : MemObject(p),
132      tickEvent(this),
133      cachePort("test", this),
134      funcPort("functional", this),
135      retryPkt(NULL),
136//      mainMem(main_mem),
137//      checkMem(check_mem),
138      size(p->memory_size),
139      percentReads(p->percent_reads),
140      percentFunctional(p->percent_functional),
141      percentUncacheable(p->percent_uncacheable),
142      issueDmas(p->issue_dmas),
143      progressInterval(p->progress_interval),
144      nextProgressMessage(p->progress_interval),
145      percentSourceUnaligned(p->percent_source_unaligned),
146      percentDestUnaligned(p->percent_dest_unaligned),
147      maxLoads(p->max_loads),
148      atomic(p->atomic)
149{
150
151    vector<string> cmd;
152    cmd.push_back("/bin/ls");
153    vector<string> null_vec;
154    //  thread = new SimpleThread(NULL, 0, NULL, 0, mainMem);
155    curTick = 0;
156
157    cachePort.snoopRangeSent = false;
158    funcPort.snoopRangeSent = true;
159
160    id = TESTER_ALLOCATOR++;
161
162    // Needs to be masked off once we know the block size.
163    traceBlockAddr = p->trace_addr;
164    baseAddr1 = 0x100000;
165    baseAddr2 = 0x400000;
166    uncacheAddr = 0x800000;
167
168    // set up counters
169    noResponseCycles = 0;
170    numReads = 0;
171    schedule(tickEvent, 0);
172
173    accessRetry = false;
174    dmaOutstanding = false;
175}
176
177Port *
178MemTest::getPort(const std::string &if_name, int idx)
179{
180    if (if_name == "functional")
181        return &funcPort;
182    else if (if_name == "test")
183        return &cachePort;
184    else
185        panic("No Such Port\n");
186}
187
188void
189MemTest::init()
190{
191    // By the time init() is called, the ports should be hooked up.
192    blockSize = cachePort.peerBlockSize();
193    blockAddrMask = blockSize - 1;
194    traceBlockAddr = blockAddr(traceBlockAddr);
195
196    // initial memory contents for both physical memory and functional
197    // memory should be 0; no need to initialize them.
198}
199
200
201void
202MemTest::completeRequest(PacketPtr pkt)
203{
204    Request *req = pkt->req;
205
206    if (issueDmas) {
207        dmaOutstanding = false;
208    }
209
210    DPRINTF(MemTest, "completing %s at address %x (blk %x)\n",
211            pkt->isWrite() ? "write" : "read",
212            req->getPaddr(), blockAddr(req->getPaddr()));
213
214    MemTestSenderState *state =
215        dynamic_cast<MemTestSenderState *>(pkt->senderState);
216
217    uint8_t *data = state->data;
218    uint8_t *pkt_data = pkt->getPtr<uint8_t>();
219
220    //Remove the address from the list of outstanding
221    std::set<unsigned>::iterator removeAddr =
222        outstandingAddrs.find(req->getPaddr());
223    assert(removeAddr != outstandingAddrs.end());
224    outstandingAddrs.erase(removeAddr);
225
226    if (pkt->isRead()) {
227        if (memcmp(pkt_data, data, pkt->getSize()) != 0) {
228            panic("%s: read of %x (blk %x) @ cycle %d "
229                  "returns %x, expected %x\n", name(),
230                  req->getPaddr(), blockAddr(req->getPaddr()), curTick,
231                  *pkt_data, *data);
232        }
233
234        numReads++;
235        numReadsStat++;
236
237        if (numReads == (uint64_t)nextProgressMessage) {
238            ccprintf(cerr, "%s: completed %d read accesses @%d\n",
239                     name(), numReads, curTick);
240            nextProgressMessage += progressInterval;
241        }
242
243        if (maxLoads != 0 && numReads >= maxLoads)
244            exitSimLoop("maximum number of loads reached");
245    } else {
246        assert(pkt->isWrite());
247        numWritesStat++;
248    }
249
250    noResponseCycles = 0;
251    delete state;
252    delete [] data;
253    delete pkt->req;
254    delete pkt;
255}
256
257void
258MemTest::regStats()
259{
260    using namespace Stats;
261
262    numReadsStat
263        .name(name() + ".num_reads")
264        .desc("number of read accesses completed")
265        ;
266
267    numWritesStat
268        .name(name() + ".num_writes")
269        .desc("number of write accesses completed")
270        ;
271
272    numCopiesStat
273        .name(name() + ".num_copies")
274        .desc("number of copy accesses completed")
275        ;
276}
277
278void
279MemTest::tick()
280{
281    if (!tickEvent.scheduled())
282        schedule(tickEvent, curTick + ticks(1));
283
284    if (++noResponseCycles >= 500000) {
285        if (issueDmas) {
286            cerr << "DMA tester ";
287        }
288        cerr << name() << ": deadlocked at cycle " << curTick << endl;
289        fatal("");
290    }
291
292    if (accessRetry || (issueDmas && dmaOutstanding)) {
293        DPRINTF(MemTest, "MemTester waiting on accessRetry or DMA response\n");
294        return;
295    }
296
297    //make new request
298    unsigned cmd = random() % 100;
299    unsigned offset = random() % size;
300    unsigned base = random() % 2;
301    uint64_t data = random();
302    unsigned access_size = random() % 4;
303    bool uncacheable = (random() % 100) < percentUncacheable;
304
305    unsigned dma_access_size = random() % 4;
306
307    //If we aren't doing copies, use id as offset, and do a false sharing
308    //mem tester
309    //We can eliminate the lower bits of the offset, and then use the id
310    //to offset within the blks
311    offset = blockAddr(offset);
312    offset += id;
313    access_size = 0;
314    dma_access_size = 0;
315
316    Request *req = new Request();
317    Request::Flags flags;
318    Addr paddr;
319
320    if (uncacheable) {
321        flags.set(Request::UNCACHEABLE);
322        paddr = uncacheAddr + offset;
323    } else  {
324        paddr = ((base) ? baseAddr1 : baseAddr2) + offset;
325    }
326    bool do_functional = (random() % 100 < percentFunctional) && !uncacheable;
327
328    if (issueDmas) {
329        paddr &= ~((1 << dma_access_size) - 1);
330        req->setPhys(paddr, 1 << dma_access_size, flags);
331        req->setThreadContext(id,0);
332    } else {
333        paddr &= ~((1 << access_size) - 1);
334        req->setPhys(paddr, 1 << access_size, flags);
335        req->setThreadContext(id,0);
336    }
337    assert(req->getSize() == 1);
338
339    uint8_t *result = new uint8_t[8];
340
341    if (cmd < percentReads) {
342        // read
343
344        // For now we only allow one outstanding request per address
345        // per tester This means we assume CPU does write forwarding
346        // to reads that alias something in the cpu store buffer.
347        if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) {
348            delete [] result;
349            delete req;
350            return;
351        }
352
353        outstandingAddrs.insert(paddr);
354
355        // ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin
356        funcPort.readBlob(req->getPaddr(), result, req->getSize());
357
358        DPRINTF(MemTest,
359                "id %d initiating %sread at addr %x (blk %x) expecting %x\n",
360                id, do_functional ? "functional " : "", req->getPaddr(),
361                blockAddr(req->getPaddr()), *result);
362
363        PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
364        pkt->setSrc(0);
365        pkt->dataDynamicArray(new uint8_t[req->getSize()]);
366        MemTestSenderState *state = new MemTestSenderState(result);
367        pkt->senderState = state;
368
369        if (do_functional) {
370            cachePort.sendFunctional(pkt);
371            completeRequest(pkt);
372        } else {
373            sendPkt(pkt);
374        }
375    } else {
376        // write
377
378        // For now we only allow one outstanding request per addreess
379        // per tester.  This means we assume CPU does write forwarding
380        // to reads that alias something in the cpu store buffer.
381        if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) {
382            delete [] result;
383            delete req;
384            return;
385        }
386
387        outstandingAddrs.insert(paddr);
388
389        DPRINTF(MemTest, "initiating %swrite at addr %x (blk %x) value %x\n",
390                do_functional ? "functional " : "", req->getPaddr(),
391                blockAddr(req->getPaddr()), data & 0xff);
392
393        PacketPtr pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast);
394        pkt->setSrc(0);
395        uint8_t *pkt_data = new uint8_t[req->getSize()];
396        pkt->dataDynamicArray(pkt_data);
397        memcpy(pkt_data, &data, req->getSize());
398        MemTestSenderState *state = new MemTestSenderState(result);
399        pkt->senderState = state;
400
401        funcPort.writeBlob(req->getPaddr(), pkt_data, req->getSize());
402
403        if (do_functional) {
404            cachePort.sendFunctional(pkt);
405            completeRequest(pkt);
406        } else {
407            sendPkt(pkt);
408        }
409    }
410}
411
412void
413MemTest::doRetry()
414{
415    if (cachePort.sendTiming(retryPkt)) {
416        DPRINTF(MemTest, "accessRetry setting to false\n");
417        accessRetry = false;
418        retryPkt = NULL;
419    }
420}
421
422
423void
424MemTest::printAddr(Addr a)
425{
426    cachePort.printAddr(a);
427}
428
429
430MemTest *
431MemTestParams::create()
432{
433    return new MemTest(this);
434}
435