memtest.cc revision 10653:e3fc6bc7f97e
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Erik Hallnor 29 * Steve Reinhardt 30 */ 31 32// FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded 33 34#include <iomanip> 35#include <set> 36#include <string> 37#include <vector> 38 39#include "base/misc.hh" 40#include "base/random.hh" 41#include "base/statistics.hh" 42#include "cpu/testers/memtest/memtest.hh" 43#include "debug/MemTest.hh" 44#include "mem/mem_object.hh" 45#include "mem/packet.hh" 46#include "mem/port.hh" 47#include "mem/request.hh" 48#include "sim/sim_events.hh" 49#include "sim/stats.hh" 50#include "sim/system.hh" 51 52using namespace std; 53 54int TESTER_ALLOCATOR=0; 55 56bool 57MemTest::CpuPort::recvTimingResp(PacketPtr pkt) 58{ 59 memtest->completeRequest(pkt); 60 return true; 61} 62 63void 64MemTest::CpuPort::recvRetry() 65{ 66 memtest->doRetry(); 67} 68 69void 70MemTest::sendPkt(PacketPtr pkt) { 71 if (atomic) { 72 cachePort.sendAtomic(pkt); 73 completeRequest(pkt); 74 } 75 else if (!cachePort.sendTimingReq(pkt)) { 76 DPRINTF(MemTest, "accessRetry setting to true\n"); 77 78 // 79 // dma requests should never be retried 80 // 81 if (issueDmas) { 82 panic("Nacked DMA requests are not supported\n"); 83 } 84 accessRetry = true; 85 retryPkt = pkt; 86 } else { 87 if (issueDmas) { 88 dmaOutstanding = true; 89 } 90 } 91 92} 93 94MemTest::MemTest(const Params *p) 95 : MemObject(p), 96 tickEvent(this), 97 cachePort("test", this), 98 funcPort("functional", this), 99 funcProxy(funcPort, p->sys->cacheLineSize()), 100 retryPkt(NULL), 101// mainMem(main_mem), 102// checkMem(check_mem), 103 size(p->memory_size), 104 percentReads(p->percent_reads), 105 percentFunctional(p->percent_functional), 106 percentUncacheable(p->percent_uncacheable), 107 issueDmas(p->issue_dmas), 108 masterId(p->sys->getMasterId(name())), 109 blockSize(p->sys->cacheLineSize()), 110 progressInterval(p->progress_interval), 111 nextProgressMessage(p->progress_interval), 112 percentSourceUnaligned(p->percent_source_unaligned), 113 percentDestUnaligned(p->percent_dest_unaligned), 114 maxLoads(p->max_loads), 115 atomic(p->atomic), 116 suppress_func_warnings(p->suppress_func_warnings) 117{ 118 id = TESTER_ALLOCATOR++; 119 120 // Needs to be masked off once we know the block size. 121 traceBlockAddr = p->trace_addr; 122 baseAddr1 = 0x100000; 123 baseAddr2 = 0x400000; 124 uncacheAddr = 0x800000; 125 126 blockAddrMask = blockSize - 1; 127 traceBlockAddr = blockAddr(traceBlockAddr); 128 129 // set up counters 130 noResponseCycles = 0; 131 numReads = 0; 132 numWrites = 0; 133 schedule(tickEvent, 0); 134 135 accessRetry = false; 136 dmaOutstanding = false; 137} 138 139BaseMasterPort & 140MemTest::getMasterPort(const std::string &if_name, PortID idx) 141{ 142 if (if_name == "functional") 143 return funcPort; 144 else if (if_name == "test") 145 return cachePort; 146 else 147 return MemObject::getMasterPort(if_name, idx); 148} 149 150void 151MemTest::init() 152{ 153 // initial memory contents for both physical memory and functional 154 // memory should be 0; no need to initialize them. 155} 156 157 158void 159MemTest::completeRequest(PacketPtr pkt) 160{ 161 Request *req = pkt->req; 162 163 if (issueDmas) { 164 dmaOutstanding = false; 165 } 166 167 DPRINTF(MemTest, "completing %s at address %x (blk %x) %s\n", 168 pkt->isWrite() ? "write" : "read", 169 req->getPaddr(), blockAddr(req->getPaddr()), 170 pkt->isError() ? "error" : "success"); 171 172 MemTestSenderState *state = 173 safe_cast<MemTestSenderState *>(pkt->senderState); 174 175 uint8_t *data = state->data; 176 // @todo: This should really be a const pointer 177 uint8_t *pkt_data = pkt->getPtr<uint8_t>(); 178 179 //Remove the address from the list of outstanding 180 std::set<unsigned>::iterator removeAddr = 181 outstandingAddrs.find(req->getPaddr()); 182 assert(removeAddr != outstandingAddrs.end()); 183 outstandingAddrs.erase(removeAddr); 184 185 if (pkt->isError()) { 186 if (!suppress_func_warnings) { 187 warn("Functional %s access failed at %#x\n", 188 pkt->isWrite() ? "write" : "read", req->getPaddr()); 189 } 190 } else { 191 if (pkt->isRead()) { 192 if (memcmp(pkt_data, data, pkt->getSize()) != 0) { 193 panic("%s: read of %x (blk %x) @ cycle %d " 194 "returns %x, expected %x\n", name(), 195 req->getPaddr(), blockAddr(req->getPaddr()), curTick(), 196 *pkt_data, *data); 197 } 198 199 numReads++; 200 numReadsStat++; 201 202 if (numReads == (uint64_t)nextProgressMessage) { 203 ccprintf(cerr, "%s: completed %d read, %d write accesses @%d\n", 204 name(), numReads, numWrites, curTick()); 205 nextProgressMessage += progressInterval; 206 } 207 208 if (maxLoads != 0 && numReads >= maxLoads) 209 exitSimLoop("maximum number of loads reached"); 210 } else { 211 assert(pkt->isWrite()); 212 funcProxy.writeBlob(req->getPaddr(), pkt_data, req->getSize()); 213 numWrites++; 214 numWritesStat++; 215 } 216 } 217 218 noResponseCycles = 0; 219 delete state; 220 delete [] data; 221 delete pkt->req; 222 delete pkt; 223} 224 225void 226MemTest::regStats() 227{ 228 using namespace Stats; 229 230 numReadsStat 231 .name(name() + ".num_reads") 232 .desc("number of read accesses completed") 233 ; 234 235 numWritesStat 236 .name(name() + ".num_writes") 237 .desc("number of write accesses completed") 238 ; 239 240 numCopiesStat 241 .name(name() + ".num_copies") 242 .desc("number of copy accesses completed") 243 ; 244} 245 246void 247MemTest::tick() 248{ 249 if (!tickEvent.scheduled()) 250 schedule(tickEvent, clockEdge(Cycles(1))); 251 252 if (++noResponseCycles >= 500000) { 253 if (issueDmas) { 254 cerr << "DMA tester "; 255 } 256 cerr << name() << ": deadlocked at cycle " << curTick() << endl; 257 fatal(""); 258 } 259 260 if (accessRetry || (issueDmas && dmaOutstanding)) { 261 DPRINTF(MemTest, "MemTester waiting on accessRetry or DMA response\n"); 262 return; 263 } 264 265 //make new request 266 unsigned cmd = random_mt.random(0, 100); 267 unsigned offset = random_mt.random<unsigned>(0, size - 1); 268 unsigned base = random_mt.random(0, 1); 269 uint64_t data = random_mt.random<uint64_t>(); 270 unsigned access_size = random_mt.random(0, 3); 271 bool uncacheable = random_mt.random(0, 100) < percentUncacheable; 272 273 unsigned dma_access_size = random_mt.random(0, 3); 274 275 //If we aren't doing copies, use id as offset, and do a false sharing 276 //mem tester 277 //We can eliminate the lower bits of the offset, and then use the id 278 //to offset within the blks 279 offset = blockAddr(offset); 280 offset += id; 281 access_size = 0; 282 dma_access_size = 0; 283 284 Request::Flags flags; 285 Addr paddr; 286 287 if (uncacheable) { 288 flags.set(Request::UNCACHEABLE); 289 paddr = uncacheAddr + offset; 290 } else { 291 paddr = ((base) ? baseAddr1 : baseAddr2) + offset; 292 } 293 294 // For now we only allow one outstanding request per address 295 // per tester This means we assume CPU does write forwarding 296 // to reads that alias something in the cpu store buffer. 297 if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) { 298 return; 299 } 300 301 bool do_functional = (random_mt.random(0, 100) < percentFunctional) && 302 !uncacheable; 303 Request *req = nullptr; 304 uint8_t *result = new uint8_t[8]; 305 306 if (issueDmas) { 307 paddr &= ~((1 << dma_access_size) - 1); 308 req = new Request(paddr, 1 << dma_access_size, flags, masterId); 309 req->setThreadContext(id,0); 310 } else { 311 paddr &= ~((1 << access_size) - 1); 312 req = new Request(paddr, 1 << access_size, flags, masterId); 313 req->setThreadContext(id,0); 314 } 315 assert(req->getSize() == 1); 316 317 if (cmd < percentReads) { 318 // read 319 outstandingAddrs.insert(paddr); 320 321 // ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin 322 funcProxy.readBlob(req->getPaddr(), result, req->getSize()); 323 324 DPRINTF(MemTest, 325 "id %d initiating %sread at addr %x (blk %x) expecting %x\n", 326 id, do_functional ? "functional " : "", req->getPaddr(), 327 blockAddr(req->getPaddr()), *result); 328 329 PacketPtr pkt = new Packet(req, MemCmd::ReadReq); 330 pkt->dataDynamic(new uint8_t[req->getSize()]); 331 MemTestSenderState *state = new MemTestSenderState(result); 332 pkt->senderState = state; 333 334 if (do_functional) { 335 assert(pkt->needsResponse()); 336 pkt->setSuppressFuncError(); 337 cachePort.sendFunctional(pkt); 338 completeRequest(pkt); 339 } else { 340 sendPkt(pkt); 341 } 342 } else { 343 // write 344 outstandingAddrs.insert(paddr); 345 346 DPRINTF(MemTest, "initiating %swrite at addr %x (blk %x) value %x\n", 347 do_functional ? "functional " : "", req->getPaddr(), 348 blockAddr(req->getPaddr()), data & 0xff); 349 350 PacketPtr pkt = new Packet(req, MemCmd::WriteReq); 351 uint8_t *pkt_data = new uint8_t[req->getSize()]; 352 pkt->dataDynamic(pkt_data); 353 memcpy(pkt_data, &data, req->getSize()); 354 MemTestSenderState *state = new MemTestSenderState(result); 355 pkt->senderState = state; 356 357 if (do_functional) { 358 pkt->setSuppressFuncError(); 359 cachePort.sendFunctional(pkt); 360 completeRequest(pkt); 361 } else { 362 sendPkt(pkt); 363 } 364 } 365} 366 367void 368MemTest::doRetry() 369{ 370 if (cachePort.sendTimingReq(retryPkt)) { 371 DPRINTF(MemTest, "accessRetry setting to false\n"); 372 accessRetry = false; 373 retryPkt = NULL; 374 } 375} 376 377 378void 379MemTest::printAddr(Addr a) 380{ 381 cachePort.printAddr(a); 382} 383 384 385MemTest * 386MemTestParams::create() 387{ 388 return new MemTest(this); 389} 390