SeriesRequestGenerator.cc revision 10566
114028Sgiacomo.gabrielli@arm.com/*
213955Sgiacomo.gabrielli@arm.com * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
313955Sgiacomo.gabrielli@arm.com * Copyright (c) 2009-2010 Advanced Micro Devices, Inc.
413955Sgiacomo.gabrielli@arm.com * All rights reserved.
513955Sgiacomo.gabrielli@arm.com *
613955Sgiacomo.gabrielli@arm.com * Redistribution and use in source and binary forms, with or without
713955Sgiacomo.gabrielli@arm.com * modification, are permitted provided that the following conditions are
813955Sgiacomo.gabrielli@arm.com * met: redistributions of source code must retain the above copyright
913955Sgiacomo.gabrielli@arm.com * notice, this list of conditions and the following disclaimer;
1013955Sgiacomo.gabrielli@arm.com * redistributions in binary form must reproduce the above copyright
1113955Sgiacomo.gabrielli@arm.com * notice, this list of conditions and the following disclaimer in the
1213955Sgiacomo.gabrielli@arm.com * documentation and/or other materials provided with the distribution;
1313955Sgiacomo.gabrielli@arm.com * neither the name of the copyright holders nor the names of its
1413955Sgiacomo.gabrielli@arm.com * contributors may be used to endorse or promote products derived from
1513955Sgiacomo.gabrielli@arm.com * this software without specific prior written permission.
1613955Sgiacomo.gabrielli@arm.com *
1713955Sgiacomo.gabrielli@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
1813955Sgiacomo.gabrielli@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
1913955Sgiacomo.gabrielli@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
2013955Sgiacomo.gabrielli@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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2213955Sgiacomo.gabrielli@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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2613955Sgiacomo.gabrielli@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
2713955Sgiacomo.gabrielli@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2813955Sgiacomo.gabrielli@arm.com */
2913955Sgiacomo.gabrielli@arm.com
3013955Sgiacomo.gabrielli@arm.com#include "base/random.hh"
3113955Sgiacomo.gabrielli@arm.com#include "cpu/testers/directedtest/DirectedGenerator.hh"
3213955Sgiacomo.gabrielli@arm.com#include "cpu/testers/directedtest/RubyDirectedTester.hh"
3313955Sgiacomo.gabrielli@arm.com#include "cpu/testers/directedtest/SeriesRequestGenerator.hh"
3413955Sgiacomo.gabrielli@arm.com#include "debug/DirectedTest.hh"
3513955Sgiacomo.gabrielli@arm.com
3613955Sgiacomo.gabrielli@arm.comSeriesRequestGenerator::SeriesRequestGenerator(const Params *p)
3713955Sgiacomo.gabrielli@arm.com    : DirectedGenerator(p),
3813955Sgiacomo.gabrielli@arm.com      m_addr_increment_size(p->addr_increment_size),
3913955Sgiacomo.gabrielli@arm.com      m_percent_writes(p->percent_writes)
4013955Sgiacomo.gabrielli@arm.com{
4113955Sgiacomo.gabrielli@arm.com    m_status = SeriesRequestGeneratorStatus_Thinking;
4213955Sgiacomo.gabrielli@arm.com    m_active_node = 0;
4313955Sgiacomo.gabrielli@arm.com    m_address = 0x0;
4413955Sgiacomo.gabrielli@arm.com}
4513955Sgiacomo.gabrielli@arm.com
4613955Sgiacomo.gabrielli@arm.comSeriesRequestGenerator::~SeriesRequestGenerator()
4713955Sgiacomo.gabrielli@arm.com{
4813955Sgiacomo.gabrielli@arm.com}
4913955Sgiacomo.gabrielli@arm.com
5013955Sgiacomo.gabrielli@arm.combool
5113955Sgiacomo.gabrielli@arm.comSeriesRequestGenerator::initiate()
5213955Sgiacomo.gabrielli@arm.com{
5313955Sgiacomo.gabrielli@arm.com    DPRINTF(DirectedTest, "initiating request\n");
5413955Sgiacomo.gabrielli@arm.com    assert(m_status == SeriesRequestGeneratorStatus_Thinking);
5513955Sgiacomo.gabrielli@arm.com
5613955Sgiacomo.gabrielli@arm.com    MasterPort* port = m_directed_tester->getCpuPort(m_active_node);
5713955Sgiacomo.gabrielli@arm.com
5813955Sgiacomo.gabrielli@arm.com    Request::Flags flags;
5913955Sgiacomo.gabrielli@arm.com
6013955Sgiacomo.gabrielli@arm.com    // For simplicity, requests are assumed to be 1 byte-sized
6113955Sgiacomo.gabrielli@arm.com    Request *req = new Request(m_address, 1, flags, masterId);
6213955Sgiacomo.gabrielli@arm.com
6313955Sgiacomo.gabrielli@arm.com    Packet::Command cmd;
6413955Sgiacomo.gabrielli@arm.com    bool do_write = (random_mt.random(0, 100) < m_percent_writes);
6513955Sgiacomo.gabrielli@arm.com    if (do_write) {
6613955Sgiacomo.gabrielli@arm.com        cmd = MemCmd::WriteReq;
6713955Sgiacomo.gabrielli@arm.com    } else {
6813955Sgiacomo.gabrielli@arm.com        cmd = MemCmd::ReadReq;
6913955Sgiacomo.gabrielli@arm.com    }
7013955Sgiacomo.gabrielli@arm.com
7113955Sgiacomo.gabrielli@arm.com    PacketPtr pkt = new Packet(req, cmd);
7213955Sgiacomo.gabrielli@arm.com    pkt->allocate();
7313955Sgiacomo.gabrielli@arm.com
7413955Sgiacomo.gabrielli@arm.com    if (port->sendTimingReq(pkt)) {
7513955Sgiacomo.gabrielli@arm.com        DPRINTF(DirectedTest, "initiating request - successful\n");
7613955Sgiacomo.gabrielli@arm.com        m_status = SeriesRequestGeneratorStatus_Request_Pending;
7713955Sgiacomo.gabrielli@arm.com        return true;
7813955Sgiacomo.gabrielli@arm.com    } else {
7913955Sgiacomo.gabrielli@arm.com        // If the packet did not issue, must delete
8013955Sgiacomo.gabrielli@arm.com        // Note: No need to delete the data, the packet destructor
8113955Sgiacomo.gabrielli@arm.com        // will delete it
8213955Sgiacomo.gabrielli@arm.com        delete pkt->req;
8313955Sgiacomo.gabrielli@arm.com        delete pkt;
8413955Sgiacomo.gabrielli@arm.com
8513955Sgiacomo.gabrielli@arm.com        DPRINTF(DirectedTest, "failed to initiate request - sequencer not ready\n");
8613955Sgiacomo.gabrielli@arm.com        return false;
8713955Sgiacomo.gabrielli@arm.com    }
8813955Sgiacomo.gabrielli@arm.com}
8913955Sgiacomo.gabrielli@arm.com
9013955Sgiacomo.gabrielli@arm.comvoid
9113955Sgiacomo.gabrielli@arm.comSeriesRequestGenerator::performCallback(uint32_t proc, Addr address)
9213955Sgiacomo.gabrielli@arm.com{
9313955Sgiacomo.gabrielli@arm.com    assert(m_active_node == proc);
9413955Sgiacomo.gabrielli@arm.com    assert(m_address == address);
9513955Sgiacomo.gabrielli@arm.com    assert(m_status == SeriesRequestGeneratorStatus_Request_Pending);
9613955Sgiacomo.gabrielli@arm.com
9713955Sgiacomo.gabrielli@arm.com    m_status = SeriesRequestGeneratorStatus_Thinking;
9813955Sgiacomo.gabrielli@arm.com    m_active_node++;
9913955Sgiacomo.gabrielli@arm.com    if (m_active_node == m_num_cpus) {
10013955Sgiacomo.gabrielli@arm.com        //
10113955Sgiacomo.gabrielli@arm.com        // Cycle of requests completed, increment cycle completions and restart
10213955Sgiacomo.gabrielli@arm.com        // at cpu zero
10313955Sgiacomo.gabrielli@arm.com        //
10413955Sgiacomo.gabrielli@arm.com        m_directed_tester->incrementCycleCompletions();
10513955Sgiacomo.gabrielli@arm.com        m_address += m_addr_increment_size;
10613955Sgiacomo.gabrielli@arm.com        m_active_node = 0;
10713955Sgiacomo.gabrielli@arm.com    }
10813955Sgiacomo.gabrielli@arm.com}
10913955Sgiacomo.gabrielli@arm.com
11013955Sgiacomo.gabrielli@arm.comSeriesRequestGenerator *
11113955Sgiacomo.gabrielli@arm.comSeriesRequestGeneratorParams::create()
11213955Sgiacomo.gabrielli@arm.com{
11313955Sgiacomo.gabrielli@arm.com    return new SeriesRequestGenerator(this);
11413955Sgiacomo.gabrielli@arm.com}
11513955Sgiacomo.gabrielli@arm.com