SeriesRequestGenerator.cc revision 8975
19665Sandreas.hansson@arm.com/* 29665Sandreas.hansson@arm.com * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 39665Sandreas.hansson@arm.com * Copyright (c) 2009-2010 Advanced Micro Devices, Inc. 49665Sandreas.hansson@arm.com * All rights reserved. 59665Sandreas.hansson@arm.com * 69665Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 79665Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 89665Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 99665Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 109665Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 119665Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 129665Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 135353Svilas.sridharan@gmail.com * neither the name of the copyright holders nor the names of its 143395Shsul@eecs.umich.edu * contributors may be used to endorse or promote products derived from 153395Shsul@eecs.umich.edu * this software without specific prior written permission. 163395Shsul@eecs.umich.edu * 173395Shsul@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 183395Shsul@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 193395Shsul@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 203395Shsul@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 213395Shsul@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 223395Shsul@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 233395Shsul@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 243395Shsul@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 253395Shsul@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 263395Shsul@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 273395Shsul@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 283395Shsul@eecs.umich.edu */ 293395Shsul@eecs.umich.edu 303395Shsul@eecs.umich.edu#include "cpu/testers/directedtest/DirectedGenerator.hh" 313395Shsul@eecs.umich.edu#include "cpu/testers/directedtest/RubyDirectedTester.hh" 323395Shsul@eecs.umich.edu#include "cpu/testers/directedtest/SeriesRequestGenerator.hh" 333395Shsul@eecs.umich.edu#include "debug/DirectedTest.hh" 343395Shsul@eecs.umich.edu 353395Shsul@eecs.umich.eduSeriesRequestGenerator::SeriesRequestGenerator(const Params *p) 363395Shsul@eecs.umich.edu : DirectedGenerator(p) 373395Shsul@eecs.umich.edu{ 383395Shsul@eecs.umich.edu m_status = SeriesRequestGeneratorStatus_Thinking; 393395Shsul@eecs.umich.edu m_active_node = 0; 403395Shsul@eecs.umich.edu m_address = 0x0; 418920Snilay@cs.wisc.edu m_addr_increment_size = p->addr_increment_size; 428920Snilay@cs.wisc.edu m_issue_writes = p->issue_writes; 438920Snilay@cs.wisc.edu} 448920Snilay@cs.wisc.edu 457025SBrad.Beckmann@amd.comSeriesRequestGenerator::~SeriesRequestGenerator() 469520SAndreas.Sandberg@ARM.com{ 479665Sandreas.hansson@arm.com} 489520SAndreas.Sandberg@ARM.com 499520SAndreas.Sandberg@ARM.combool 509520SAndreas.Sandberg@ARM.comSeriesRequestGenerator::initiate() 519520SAndreas.Sandberg@ARM.com{ 529520SAndreas.Sandberg@ARM.com DPRINTF(DirectedTest, "initiating request\n"); 539665Sandreas.hansson@arm.com assert(m_status == SeriesRequestGeneratorStatus_Thinking); 549665Sandreas.hansson@arm.com 559665Sandreas.hansson@arm.com MasterPort* port = m_directed_tester->getCpuPort(m_active_node); 569665Sandreas.hansson@arm.com 578920Snilay@cs.wisc.edu Request::Flags flags; 588920Snilay@cs.wisc.edu 599520SAndreas.Sandberg@ARM.com // For simplicity, requests are assumed to be 1 byte-sized 609520SAndreas.Sandberg@ARM.com Request *req = new Request(m_address, 1, flags, masterId); 619520SAndreas.Sandberg@ARM.com 628920Snilay@cs.wisc.edu Packet::Command cmd; 639520SAndreas.Sandberg@ARM.com if (m_issue_writes) { 648920Snilay@cs.wisc.edu cmd = MemCmd::WriteReq; 658920Snilay@cs.wisc.edu } else { 668920Snilay@cs.wisc.edu cmd = MemCmd::ReadReq; 679790Sakash.bagdia@arm.com } 689790Sakash.bagdia@arm.com PacketPtr pkt = new Packet(req, cmd); 699790Sakash.bagdia@arm.com uint8_t* dummyData = new uint8_t; 709790Sakash.bagdia@arm.com *dummyData = 0; 719789Sakash.bagdia@arm.com pkt->dataDynamic(dummyData); 729789Sakash.bagdia@arm.com 739789Sakash.bagdia@arm.com if (port->sendTimingReq(pkt)) { 749800Snilay@cs.wisc.edu DPRINTF(DirectedTest, "initiating request - successful\n"); 759800Snilay@cs.wisc.edu m_status = SeriesRequestGeneratorStatus_Request_Pending; 769800Snilay@cs.wisc.edu return true; 779800Snilay@cs.wisc.edu } else { 789800Snilay@cs.wisc.edu // If the packet did not issue, must delete 799800Snilay@cs.wisc.edu // Note: No need to delete the data, the packet destructor 809800Snilay@cs.wisc.edu // will delete it 819800Snilay@cs.wisc.edu delete pkt->req; 829800Snilay@cs.wisc.edu delete pkt; 839800Snilay@cs.wisc.edu 849800Snilay@cs.wisc.edu DPRINTF(DirectedTest, "failed to initiate request - sequencer not ready\n"); 859800Snilay@cs.wisc.edu return false; 869800Snilay@cs.wisc.edu } 879800Snilay@cs.wisc.edu} 889800Snilay@cs.wisc.edu 899800Snilay@cs.wisc.eduvoid 909800Snilay@cs.wisc.eduSeriesRequestGenerator::performCallback(uint32_t proc, Addr address) 919800Snilay@cs.wisc.edu{ 929800Snilay@cs.wisc.edu assert(m_active_node == proc); 939800Snilay@cs.wisc.edu assert(m_address == address); 949800Snilay@cs.wisc.edu assert(m_status == SeriesRequestGeneratorStatus_Request_Pending); 958920Snilay@cs.wisc.edu 968920Snilay@cs.wisc.edu m_status = SeriesRequestGeneratorStatus_Thinking; 978920Snilay@cs.wisc.edu m_active_node++; 988920Snilay@cs.wisc.edu if (m_active_node == m_num_cpus) { 998920Snilay@cs.wisc.edu // 1008920Snilay@cs.wisc.edu // Cycle of requests completed, increment cycle completions and restart 1018920Snilay@cs.wisc.edu // at cpu zero 1028920Snilay@cs.wisc.edu // 1038920Snilay@cs.wisc.edu m_directed_tester->incrementCycleCompletions(); 1048920Snilay@cs.wisc.edu m_address += m_addr_increment_size; 1058920Snilay@cs.wisc.edu m_active_node = 0; 1068920Snilay@cs.wisc.edu } 1079800Snilay@cs.wisc.edu} 1089800Snilay@cs.wisc.edu 1098920Snilay@cs.wisc.eduSeriesRequestGenerator * 1103395Shsul@eecs.umich.eduSeriesRequestGeneratorParams::create() 1118920Snilay@cs.wisc.edu{ 1128920Snilay@cs.wisc.edu return new SeriesRequestGenerator(this); 1138920Snilay@cs.wisc.edu} 1148920Snilay@cs.wisc.edu