SeriesRequestGenerator.cc revision 7553
14403Srdreslin@umich.edu/* 21693Sstever@eecs.umich.edu * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 31693Sstever@eecs.umich.edu * Copyright (c) 2009-2010 Advanced Micro Devices, Inc. 41693Sstever@eecs.umich.edu * All rights reserved. 51693Sstever@eecs.umich.edu * 61693Sstever@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 71693Sstever@eecs.umich.edu * modification, are permitted provided that the following conditions are 81693Sstever@eecs.umich.edu * met: redistributions of source code must retain the above copyright 91693Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 101693Sstever@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 111693Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 121693Sstever@eecs.umich.edu * documentation and/or other materials provided with the distribution; 131693Sstever@eecs.umich.edu * neither the name of the copyright holders nor the names of its 141693Sstever@eecs.umich.edu * contributors may be used to endorse or promote products derived from 151693Sstever@eecs.umich.edu * this software without specific prior written permission. 161693Sstever@eecs.umich.edu * 171693Sstever@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 181693Sstever@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 191693Sstever@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 201693Sstever@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 211693Sstever@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 221693Sstever@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 231693Sstever@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 241693Sstever@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 251693Sstever@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 261693Sstever@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 271693Sstever@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 281693Sstever@eecs.umich.edu */ 293358Srdreslin@umich.edu 303358Srdreslin@umich.edu#include "cpu/directedtest/RubyDirectedTester.hh" 311516SN/A#include "cpu/directedtest/DirectedGenerator.hh" 326654Snate@binkert.org#include "cpu/directedtest/SeriesRequestGenerator.hh" 336654Snate@binkert.org 346654Snate@binkert.orgSeriesRequestGenerator::SeriesRequestGenerator(const Params *p) 356654Snate@binkert.org : DirectedGenerator(p) 363358Srdreslin@umich.edu{ 373358Srdreslin@umich.edu m_status = SeriesRequestGeneratorStatus_Thinking; 386654Snate@binkert.org m_active_node = 0; 396654Snate@binkert.org m_address = 0x0; 401516SN/A m_addr_increment_size = p->addr_increment_size; 413358Srdreslin@umich.edu m_issue_writes = p->issue_writes; 423358Srdreslin@umich.edu} 433358Srdreslin@umich.edu 443358Srdreslin@umich.eduSeriesRequestGenerator::~SeriesRequestGenerator() 453358Srdreslin@umich.edu{ 463358Srdreslin@umich.edu} 473358Srdreslin@umich.edu 483358Srdreslin@umich.edubool 493358Srdreslin@umich.eduSeriesRequestGenerator::initiate() 503358Srdreslin@umich.edu{ 513358Srdreslin@umich.edu DPRINTF(DirectedTest, "initiating request\n"); 523358Srdreslin@umich.edu assert(m_status == SeriesRequestGeneratorStatus_Thinking); 533360Srdreslin@umich.edu 543358Srdreslin@umich.edu RubyDirectedTester::CpuPort* port = 553360Srdreslin@umich.edu safe_cast<RubyDirectedTester::CpuPort*>(m_directed_tester-> 563360Srdreslin@umich.edu getCpuPort(m_active_node)); 573360Srdreslin@umich.edu 585255Ssaidi@eecs.umich.edu Request::Flags flags; 593360Srdreslin@umich.edu 603360Srdreslin@umich.edu // For simplicity, requests are assumed to be 1 byte-sized 613360Srdreslin@umich.edu Request *req = new Request(m_address, 1, flags); 625255Ssaidi@eecs.umich.edu 633358Srdreslin@umich.edu Packet::Command cmd; 644403Srdreslin@umich.edu if (m_issue_writes) { 653360Srdreslin@umich.edu cmd = MemCmd::WriteReq; 663358Srdreslin@umich.edu } else { 673358Srdreslin@umich.edu cmd = MemCmd::ReadReq; 683358Srdreslin@umich.edu } 693358Srdreslin@umich.edu PacketPtr pkt = new Packet(req, cmd, m_active_node); 703358Srdreslin@umich.edu uint8_t* dummyData = new uint8_t; 713358Srdreslin@umich.edu *dummyData = 0; 723358Srdreslin@umich.edu pkt->dataDynamic(dummyData); 733358Srdreslin@umich.edu 743358Srdreslin@umich.edu if (port->sendTiming(pkt)) { 753360Srdreslin@umich.edu DPRINTF(DirectedTest, "initiating request - successful\n"); 763360Srdreslin@umich.edu m_status = SeriesRequestGeneratorStatus_Request_Pending; 773360Srdreslin@umich.edu return true; 783360Srdreslin@umich.edu } else { 793358Srdreslin@umich.edu // If the packet did not issue, must delete 803358Srdreslin@umich.edu // Note: No need to delete the data, the packet destructor 813358Srdreslin@umich.edu // will delete it 823358Srdreslin@umich.edu delete pkt->req; 834403Srdreslin@umich.edu delete pkt; 844403Srdreslin@umich.edu 855256Ssaidi@eecs.umich.edu DPRINTF(DirectedTest, "failed to initiate request - sequencer not ready\n"); 865255Ssaidi@eecs.umich.edu return false; 873358Srdreslin@umich.edu } 883358Srdreslin@umich.edu} 894403Srdreslin@umich.edu 904403Srdreslin@umich.eduvoid 915255Ssaidi@eecs.umich.eduSeriesRequestGenerator::performCallback(uint proc, Addr address) 923358Srdreslin@umich.edu{ 933358Srdreslin@umich.edu assert(m_active_node == proc); 944403Srdreslin@umich.edu assert(m_address == address); 955255Ssaidi@eecs.umich.edu assert(m_status == SeriesRequestGeneratorStatus_Request_Pending); 964403Srdreslin@umich.edu 973358Srdreslin@umich.edu m_status = SeriesRequestGeneratorStatus_Thinking; 983358Srdreslin@umich.edu m_active_node++; 994403Srdreslin@umich.edu if (m_active_node == m_num_cpus) { 1005255Ssaidi@eecs.umich.edu // 1014403Srdreslin@umich.edu // Cycle of requests completed, increment cycle completions and restart 1023358Srdreslin@umich.edu // at cpu zero 1033358Srdreslin@umich.edu // 1044403Srdreslin@umich.edu m_directed_tester->incrementCycleCompletions(); 1055255Ssaidi@eecs.umich.edu m_address += m_addr_increment_size; 1064403Srdreslin@umich.edu m_active_node = 0; 1073358Srdreslin@umich.edu } 1083358Srdreslin@umich.edu} 1094403Srdreslin@umich.edu 1105255Ssaidi@eecs.umich.eduSeriesRequestGenerator * 1114403Srdreslin@umich.eduSeriesRequestGeneratorParams::create() 1124403Srdreslin@umich.edu{ 1133358Srdreslin@umich.edu return new SeriesRequestGenerator(this); 1143358Srdreslin@umich.edu} 1154403Srdreslin@umich.edu