RubyDirectedTester.py revision 9365:644be05ee7c2 
1# Copyright (c) 2010 Advanced Micro Devices, Inc.
2# All rights reserved.
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15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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26#
27# Authors: Brad Beckmann
28
29from m5.SimObject import SimObject
30from MemObject import MemObject
31from m5.params import *
32from m5.proxy import *
33
34class DirectedGenerator(SimObject):
35    type = 'DirectedGenerator'
36    abstract = True
37    cxx_header = "cpu/testers/directedtest/DirectedGenerator.hh"
38    num_cpus = Param.Int("num of cpus")
39    system = Param.System(Parent.any, "System we belong to")
40
41class SeriesRequestGenerator(DirectedGenerator):
42    type = 'SeriesRequestGenerator'
43    cxx_header = "cpu/testers/directedtest/SeriesRequestGenerator.hh"
44    addr_increment_size = Param.Int(64, "address increment size")
45    num_series = Param.UInt32(1,
46        "number of different address streams to generate")
47    percent_writes = Param.Percent(50, "percent of access that are writes")
48
49class InvalidateGenerator(DirectedGenerator):
50    type = 'InvalidateGenerator'
51    cxx_header = "cpu/testers/directedtest/InvalidateGenerator.hh"
52    addr_increment_size = Param.Int(64, "address increment size")
53
54class RubyDirectedTester(MemObject):
55    type = 'RubyDirectedTester'
56    cxx_header = "cpu/testers/directedtest/RubyDirectedTester.hh"
57    cpuPort = VectorMasterPort("the cpu ports")
58    requests_to_complete = Param.Int("checks to complete")
59    generator = Param.DirectedGenerator("the request generator")
60