RubyDirectedTester.py revision 7553 
1# Copyright (c) 2010 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
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8# redistributions in binary form must reproduce the above copyright
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11# neither the name of the copyright holders nor the names of its
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13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Brad Beckmann
28
29from m5.SimObject import SimObject
30from MemObject import MemObject
31from m5.params import *
32from m5.proxy import *
33
34class DirectedGenerator(SimObject):
35    type = 'DirectedGenerator'
36    abstract = True
37    num_cpus = Param.Int("num of cpus")
38
39class SeriesRequestGenerator(DirectedGenerator):
40    type = 'SeriesRequestGenerator'
41    addr_increment_size = Param.Int(64, "address increment size")
42    issue_writes = Param.Bool(True, "issue writes if true, otherwise reads")
43
44class InvalidateGenerator(DirectedGenerator):
45    type = 'InvalidateGenerator'
46    addr_increment_size = Param.Int(64, "address increment size")
47
48class RubyDirectedTester(MemObject):
49    type = 'RubyDirectedTester'
50    cpuPort = VectorPort("the cpu ports")
51    requests_to_complete = Param.Int("checks to complete")
52    generator = Param.DirectedGenerator("the request generator")
53