RubyDirectedTester.py revision 9365
12391SN/A# Copyright (c) 2010 Advanced Micro Devices, Inc. 28719SAli.Saidi@ARM.com# All rights reserved. 37733SAli.Saidi@ARM.com# 47733SAli.Saidi@ARM.com# Redistribution and use in source and binary forms, with or without 57733SAli.Saidi@ARM.com# modification, are permitted provided that the following conditions are 67733SAli.Saidi@ARM.com# met: redistributions of source code must retain the above copyright 77733SAli.Saidi@ARM.com# notice, this list of conditions and the following disclaimer; 87733SAli.Saidi@ARM.com# redistributions in binary form must reproduce the above copyright 97733SAli.Saidi@ARM.com# notice, this list of conditions and the following disclaimer in the 107733SAli.Saidi@ARM.com# documentation and/or other materials provided with the distribution; 117733SAli.Saidi@ARM.com# neither the name of the copyright holders nor the names of its 127733SAli.Saidi@ARM.com# contributors may be used to endorse or promote products derived from 137733SAli.Saidi@ARM.com# this software without specific prior written permission. 142391SN/A# 152391SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162391SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172391SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182391SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192391SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202391SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212391SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222391SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232391SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242391SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252391SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262391SN/A# 272391SN/A# Authors: Brad Beckmann 282391SN/A 292391SN/Afrom m5.SimObject import SimObject 302391SN/Afrom MemObject import MemObject 312391SN/Afrom m5.params import * 322391SN/Afrom m5.proxy import * 332391SN/A 342391SN/Aclass DirectedGenerator(SimObject): 352391SN/A type = 'DirectedGenerator' 362391SN/A abstract = True 372391SN/A cxx_header = "cpu/testers/directedtest/DirectedGenerator.hh" 382391SN/A num_cpus = Param.Int("num of cpus") 392665Ssaidi@eecs.umich.edu system = Param.System(Parent.any, "System we belong to") 402665Ssaidi@eecs.umich.edu 412914Ssaidi@eecs.umich.educlass SeriesRequestGenerator(DirectedGenerator): 422391SN/A type = 'SeriesRequestGenerator' 432391SN/A cxx_header = "cpu/testers/directedtest/SeriesRequestGenerator.hh" 448229Snate@binkert.org addr_increment_size = Param.Int(64, "address increment size") 452391SN/A num_series = Param.UInt32(1, 467730SAli.Saidi@ARM.com "number of different address streams to generate") 472391SN/A percent_writes = Param.Percent(50, "percent of access that are writes") 482391SN/A 492391SN/Aclass InvalidateGenerator(DirectedGenerator): 502391SN/A type = 'InvalidateGenerator' 518229Snate@binkert.org cxx_header = "cpu/testers/directedtest/InvalidateGenerator.hh" 526712Snate@binkert.org addr_increment_size = Param.Int(64, "address increment size") 532391SN/A 542391SN/Aclass RubyDirectedTester(MemObject): 552391SN/A type = 'RubyDirectedTester' 568066SAli.Saidi@ARM.com cxx_header = "cpu/testers/directedtest/RubyDirectedTester.hh" 576329Sgblack@eecs.umich.edu cpuPort = VectorMasterPort("the cpu ports") 587730SAli.Saidi@ARM.com requests_to_complete = Param.Int("checks to complete") 592391SN/A generator = Param.DirectedGenerator("the request generator") 605399Ssaidi@eecs.umich.edu