RubyDirectedTester.py revision 8839
17553SN/A# Copyright (c) 2010 Advanced Micro Devices, Inc. 27553SN/A# All rights reserved. 37553SN/A# 47553SN/A# Redistribution and use in source and binary forms, with or without 57553SN/A# modification, are permitted provided that the following conditions are 67553SN/A# met: redistributions of source code must retain the above copyright 77553SN/A# notice, this list of conditions and the following disclaimer; 87553SN/A# redistributions in binary form must reproduce the above copyright 97553SN/A# notice, this list of conditions and the following disclaimer in the 107553SN/A# documentation and/or other materials provided with the distribution; 117553SN/A# neither the name of the copyright holders nor the names of its 127553SN/A# contributors may be used to endorse or promote products derived from 137553SN/A# this software without specific prior written permission. 147553SN/A# 157553SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 167553SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 177553SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 187553SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 197553SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 207553SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 217553SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 227553SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 237553SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 247553SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 257553SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 267553SN/A# 277553SN/A# Authors: Brad Beckmann 287553SN/A 297553SN/Afrom m5.SimObject import SimObject 307553SN/Afrom MemObject import MemObject 317553SN/Afrom m5.params import * 327553SN/Afrom m5.proxy import * 337553SN/A 347553SN/Aclass DirectedGenerator(SimObject): 357553SN/A type = 'DirectedGenerator' 367553SN/A abstract = True 377553SN/A num_cpus = Param.Int("num of cpus") 388832SAli.Saidi@ARM.com system = Param.System(Parent.any, "System we belong to") 397553SN/A 407553SN/Aclass SeriesRequestGenerator(DirectedGenerator): 417553SN/A type = 'SeriesRequestGenerator' 427553SN/A addr_increment_size = Param.Int(64, "address increment size") 437553SN/A issue_writes = Param.Bool(True, "issue writes if true, otherwise reads") 447553SN/A 457553SN/Aclass InvalidateGenerator(DirectedGenerator): 467553SN/A type = 'InvalidateGenerator' 477553SN/A addr_increment_size = Param.Int(64, "address increment size") 487553SN/A 497553SN/Aclass RubyDirectedTester(MemObject): 507553SN/A type = 'RubyDirectedTester' 518839Sandreas.hansson@arm.com cpuPort = VectorMasterPort("the cpu ports") 527553SN/A requests_to_complete = Param.Int("checks to complete") 537553SN/A generator = Param.DirectedGenerator("the request generator") 54