static_inst.hh revision 1416
12155SN/A/* 22155SN/A * Copyright (c) 2003-2004 The Regents of The University of Michigan 32155SN/A * All rights reserved. 42155SN/A * 52155SN/A * Redistribution and use in source and binary forms, with or without 62155SN/A * modification, are permitted provided that the following conditions are 72155SN/A * met: redistributions of source code must retain the above copyright 82155SN/A * notice, this list of conditions and the following disclaimer; 92155SN/A * redistributions in binary form must reproduce the above copyright 102155SN/A * notice, this list of conditions and the following disclaimer in the 112155SN/A * documentation and/or other materials provided with the distribution; 122155SN/A * neither the name of the copyright holders nor the names of its 132155SN/A * contributors may be used to endorse or promote products derived from 142155SN/A * this software without specific prior written permission. 152155SN/A * 162155SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172155SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182155SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192155SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202155SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212155SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222155SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232155SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242155SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252155SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262155SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272155SN/A */ 282665Ssaidi@eecs.umich.edu 292665Ssaidi@eecs.umich.edu#ifndef __STATIC_INST_HH__ 302155SN/A#define __STATIC_INST_HH__ 314202Sbinkertn@umich.edu 322155SN/A#include <bitset> 332178SN/A#include <string> 342178SN/A 352178SN/A#include "sim/host.hh" 362178SN/A#include "base/hashmap.hh" 372178SN/A#include "base/refcnt.hh" 382178SN/A 392178SN/A#include "cpu/full_cpu/op_class.hh" 402178SN/A#include "targetarch/isa_traits.hh" 412178SN/A 422178SN/A// forward declarations 432178SN/Aclass ExecContext; 442178SN/Aclass DynInst; 452155SN/Aclass FastCPU; 462178SN/Aclass SimpleCPU; 472155SN/Aclass InorderCPU; 482155SN/Aclass SymbolTable; 492178SN/A 502155SN/Anamespace Trace { 515865Sksewell@umich.edu class InstRecord; 526181Sksewell@umich.edu} 536181Sksewell@umich.edu 545865Sksewell@umich.edu/** 553918Ssaidi@eecs.umich.edu * Base, ISA-independent static instruction class. 565865Sksewell@umich.edu * 572623SN/A * The main component of this class is the vector of flags and the 583918Ssaidi@eecs.umich.edu * associated methods for reading them. Any object that can rely 595865Sksewell@umich.edu * solely on these flags can process instructions without being 605865Sksewell@umich.edu * recompiled for multiple ISAs. 612155SN/A */ 622155SN/Aclass StaticInstBase : public RefCounted 632292SN/A{ 646181Sksewell@umich.edu protected: 656181Sksewell@umich.edu 663918Ssaidi@eecs.umich.edu /// Set of boolean static instruction properties. 672292SN/A /// 682292SN/A /// Notes: 692292SN/A /// - The IsInteger and IsFloating flags are based on the class of 703918Ssaidi@eecs.umich.edu /// registers accessed by the instruction. Although most 712292SN/A /// instructions will have exactly one of these two flags set, it 722292SN/A /// is possible for an instruction to have neither (e.g., direct 732766Sktlim@umich.edu /// unconditional branches, memory barriers) or both (e.g., an 742766Sktlim@umich.edu /// FP/int conversion). 752766Sktlim@umich.edu /// - If IsMemRef is set, then exactly one of IsLoad or IsStore 762921Sktlim@umich.edu /// will be set. 772921Sktlim@umich.edu /// - If IsControl is set, then exactly one of IsDirectControl or 782766Sktlim@umich.edu /// IsIndirect Control will be set, and exactly one of 792766Sktlim@umich.edu /// IsCondControl or IsUncondControl will be set. 805529Snate@binkert.org /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are 812766Sktlim@umich.edu /// implemented as flags since in the current model there's no 824762Snate@binkert.org /// other way for instructions to inject behavior into the 832155SN/A /// pipeline outside of fetch. Once we go to an exec-in-exec CPU 842155SN/A /// model we should be able to get rid of these flags and 852155SN/A /// implement this behavior via the execute() methods. 862155SN/A /// 872155SN/A enum Flags { 882155SN/A IsNop, ///< Is a no-op (no effect at all). 892766Sktlim@umich.edu 902155SN/A IsInteger, ///< References integer regs. 915865Sksewell@umich.edu IsFloating, ///< References FP regs. 922155SN/A 932155SN/A IsMemRef, ///< References memory (load, store, or prefetch). 942155SN/A IsLoad, ///< Reads from memory (load or prefetch). 952155SN/A IsStore, ///< Writes to memory. 962178SN/A IsInstPrefetch, ///< Instruction-cache prefetch. 972178SN/A IsDataPrefetch, ///< Data-cache prefetch. 982178SN/A IsCopy, ///< Fast Cache block copy 992766Sktlim@umich.edu 1002178SN/A IsControl, ///< Control transfer instruction. 1012178SN/A IsDirectControl, ///< PC relative control transfer. 1022178SN/A IsIndirectControl, ///< Register indirect control transfer. 1032178SN/A IsCondControl, ///< Conditional control transfer. 1042766Sktlim@umich.edu IsUncondControl, ///< Unconditional control transfer. 1052766Sktlim@umich.edu IsCall, ///< Subroutine call. 1062766Sktlim@umich.edu IsReturn, ///< Subroutine return. 1072788Sktlim@umich.edu 1082178SN/A IsThreadSync, ///< Thread synchronization operation. 1092733Sktlim@umich.edu 1102733Sktlim@umich.edu IsSerializing, ///< Serializes pipeline: won't execute until all 1112817Sksewell@umich.edu /// older instructions have committed. 1122733Sktlim@umich.edu IsMemBarrier, ///< Is a memory barrier 1134486Sbinkertn@umich.edu IsWriteBarrier, ///< Is a write barrier 1144486Sbinkertn@umich.edu 1154776Sgblack@eecs.umich.edu IsNonSpeculative, ///< Should not be executed speculatively 1164776Sgblack@eecs.umich.edu 1174486Sbinkertn@umich.edu NumFlags 1184202Sbinkertn@umich.edu }; 1194202Sbinkertn@umich.edu 1204202Sbinkertn@umich.edu /// Flag values for this instruction. 1214202Sbinkertn@umich.edu std::bitset<NumFlags> flags; 1224202Sbinkertn@umich.edu 1234776Sgblack@eecs.umich.edu /// See opClass(). 1244202Sbinkertn@umich.edu OpClass _opClass; 1254202Sbinkertn@umich.edu 1264202Sbinkertn@umich.edu /// See numSrcRegs(). 1274202Sbinkertn@umich.edu int8_t _numSrcRegs; 1285217Ssaidi@eecs.umich.edu 1294202Sbinkertn@umich.edu /// See numDestRegs(). 1302155SN/A int8_t _numDestRegs; 1314202Sbinkertn@umich.edu 1324486Sbinkertn@umich.edu /// The following are used to track physical register usage 1334486Sbinkertn@umich.edu /// for machines with separate int & FP reg files. 1344202Sbinkertn@umich.edu //@{ 1354202Sbinkertn@umich.edu int8_t _numFPDestRegs; 1362821Sktlim@umich.edu int8_t _numIntDestRegs; 1374776Sgblack@eecs.umich.edu //@} 1384776Sgblack@eecs.umich.edu 1394776Sgblack@eecs.umich.edu /// Constructor. 1404776Sgblack@eecs.umich.edu /// It's important to initialize everything here to a sane 1414776Sgblack@eecs.umich.edu /// default, since the decoder generally only overrides 1424776Sgblack@eecs.umich.edu /// the fields that are meaningful for the particular 1434776Sgblack@eecs.umich.edu /// instruction. 1444776Sgblack@eecs.umich.edu StaticInstBase(OpClass __opClass) 1452766Sktlim@umich.edu : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0), 1464202Sbinkertn@umich.edu _numFPDestRegs(0), _numIntDestRegs(0) 1475192Ssaidi@eecs.umich.edu { 1482733Sktlim@umich.edu } 1492733Sktlim@umich.edu 1502733Sktlim@umich.edu public: 1512733Sktlim@umich.edu 1522733Sktlim@umich.edu /// @name Register information. 1532874Sktlim@umich.edu /// The sum of numFPDestRegs() and numIntDestRegs() equals 1542874Sktlim@umich.edu /// numDestRegs(). The former two functions are used to track 1552874Sktlim@umich.edu /// physical register usage for machines with separate int & FP 1564202Sbinkertn@umich.edu /// reg files. 1572733Sktlim@umich.edu //@{ 1585192Ssaidi@eecs.umich.edu /// Number of source registers. 1595192Ssaidi@eecs.umich.edu int8_t numSrcRegs() const { return _numSrcRegs; } 1605192Ssaidi@eecs.umich.edu /// Number of destination registers. 1615217Ssaidi@eecs.umich.edu int8_t numDestRegs() const { return _numDestRegs; } 1625192Ssaidi@eecs.umich.edu /// Number of floating-point destination regs. 1635192Ssaidi@eecs.umich.edu int8_t numFPDestRegs() const { return _numFPDestRegs; } 1645192Ssaidi@eecs.umich.edu /// Number of integer destination regs. 1655192Ssaidi@eecs.umich.edu int8_t numIntDestRegs() const { return _numIntDestRegs; } 1665192Ssaidi@eecs.umich.edu //@} 1675192Ssaidi@eecs.umich.edu 1685192Ssaidi@eecs.umich.edu /// @name Flag accessors. 1695192Ssaidi@eecs.umich.edu /// These functions are used to access the values of the various 1705192Ssaidi@eecs.umich.edu /// instruction property flags. See StaticInstBase::Flags for descriptions 1715192Ssaidi@eecs.umich.edu /// of the individual flags. 1725192Ssaidi@eecs.umich.edu //@{ 1735192Ssaidi@eecs.umich.edu 1745192Ssaidi@eecs.umich.edu bool isNop() const { return flags[IsNop]; } 1755784Sgblack@eecs.umich.edu 1765784Sgblack@eecs.umich.edu bool isMemRef() const { return flags[IsMemRef]; } 1775192Ssaidi@eecs.umich.edu bool isLoad() const { return flags[IsLoad]; } 1785192Ssaidi@eecs.umich.edu bool isStore() const { return flags[IsStore]; } 1795192Ssaidi@eecs.umich.edu bool isInstPrefetch() const { return flags[IsInstPrefetch]; } 1805192Ssaidi@eecs.umich.edu bool isDataPrefetch() const { return flags[IsDataPrefetch]; } 1815192Ssaidi@eecs.umich.edu bool isCopy() const { return flags[IsCopy];} 1825192Ssaidi@eecs.umich.edu 1835784Sgblack@eecs.umich.edu bool isInteger() const { return flags[IsInteger]; } 1846036Sksewell@umich.edu bool isFloating() const { return flags[IsFloating]; } 1856036Sksewell@umich.edu 186 bool isControl() const { return flags[IsControl]; } 187 bool isCall() const { return flags[IsCall]; } 188 bool isReturn() const { return flags[IsReturn]; } 189 bool isDirectCtrl() const { return flags[IsDirectControl]; } 190 bool isIndirectCtrl() const { return flags[IsIndirectControl]; } 191 bool isCondCtrl() const { return flags[IsCondControl]; } 192 bool isUncondCtrl() const { return flags[IsUncondControl]; } 193 194 bool isThreadSync() const { return flags[IsThreadSync]; } 195 bool isSerializing() const { return flags[IsSerializing]; } 196 bool isMemBarrier() const { return flags[IsMemBarrier]; } 197 bool isWriteBarrier() const { return flags[IsWriteBarrier]; } 198 bool isNonSpeculative() const { return flags[IsNonSpeculative]; } 199 //@} 200 201 /// Operation class. Used to select appropriate function unit in issue. 202 OpClass opClass() const { return _opClass; } 203}; 204 205 206// forward declaration 207template <class ISA> 208class StaticInstPtr; 209 210/** 211 * Generic yet ISA-dependent static instruction class. 212 * 213 * This class builds on StaticInstBase, defining fields and interfaces 214 * that are generic across all ISAs but that differ in details 215 * according to the specific ISA being used. 216 */ 217template <class ISA> 218class StaticInst : public StaticInstBase 219{ 220 public: 221 222 /// Binary machine instruction type. 223 typedef typename ISA::MachInst MachInst; 224 /// Memory address type. 225 typedef typename ISA::Addr Addr; 226 /// Logical register index type. 227 typedef typename ISA::RegIndex RegIndex; 228 229 enum { 230 MaxInstSrcRegs = ISA::MaxInstSrcRegs, //< Max source regs 231 MaxInstDestRegs = ISA::MaxInstDestRegs, //< Max dest regs 232 }; 233 234 235 /// Return logical index (architectural reg num) of i'th destination reg. 236 /// Only the entries from 0 through numDestRegs()-1 are valid. 237 RegIndex destRegIdx(int i) const { return _destRegIdx[i]; } 238 239 /// Return logical index (architectural reg num) of i'th source reg. 240 /// Only the entries from 0 through numSrcRegs()-1 are valid. 241 RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; } 242 243 /// Pointer to a statically allocated "null" instruction object. 244 /// Used to give eaCompInst() and memAccInst() something to return 245 /// when called on non-memory instructions. 246 static StaticInstPtr<ISA> nullStaticInstPtr; 247 248 /** 249 * Memory references only: returns "fake" instruction representing 250 * the effective address part of the memory operation. Used to 251 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for 252 * just the EA computation. 253 */ 254 virtual const 255 StaticInstPtr<ISA> &eaCompInst() const { return nullStaticInstPtr; } 256 257 /** 258 * Memory references only: returns "fake" instruction representing 259 * the memory access part of the memory operation. Used to 260 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for 261 * just the memory access (not the EA computation). 262 */ 263 virtual const 264 StaticInstPtr<ISA> &memAccInst() const { return nullStaticInstPtr; } 265 266 /// The binary machine instruction. 267 const MachInst machInst; 268 269 protected: 270 271 /// See destRegIdx(). 272 RegIndex _destRegIdx[MaxInstDestRegs]; 273 /// See srcRegIdx(). 274 RegIndex _srcRegIdx[MaxInstSrcRegs]; 275 276 /** 277 * Base mnemonic (e.g., "add"). Used by generateDisassembly() 278 * methods. Also useful to readily identify instructions from 279 * within the debugger when #cachedDisassembly has not been 280 * initialized. 281 */ 282 const char *mnemonic; 283 284 /** 285 * String representation of disassembly (lazily evaluated via 286 * disassemble()). 287 */ 288 mutable std::string *cachedDisassembly; 289 290 /** 291 * Internal function to generate disassembly string. 292 */ 293 virtual std::string 294 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0; 295 296 /// Constructor. 297 StaticInst(const char *_mnemonic, MachInst _machInst, OpClass __opClass) 298 : StaticInstBase(__opClass), 299 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0) 300 { 301 } 302 303 public: 304 305 virtual ~StaticInst() 306 { 307 if (cachedDisassembly) 308 delete cachedDisassembly; 309 } 310 311 /** 312 * Execute this instruction under SimpleCPU model. 313 */ 314 virtual Fault execute(SimpleCPU *xc, 315 Trace::InstRecord *traceData) const = 0; 316 317 /** 318 * Execute this instruction under InorderCPU model. 319 */ 320 virtual Fault execute(InorderCPU *xc, 321 Trace::InstRecord *traceData) const = 0; 322 323 324 /** 325 * Execute this instruction under FastCPU model. 326 */ 327 virtual Fault execute(FastCPU *xc, 328 Trace::InstRecord *traceData) const = 0; 329 330 /** 331 * Execute this instruction under detailed FullCPU model. 332 */ 333 virtual Fault execute(DynInst *xc, 334 Trace::InstRecord *traceData) const = 0; 335 336 /** 337 * Return the target address for a PC-relative branch. 338 * Invalid if not a PC-relative branch (i.e. isDirectCtrl() 339 * should be true). 340 */ 341 virtual Addr branchTarget(Addr branchPC) const 342 { 343 panic("StaticInst::branchTarget() called on instruction " 344 "that is not a PC-relative branch."); 345 } 346 347 /** 348 * Return the target address for an indirect branch (jump). The 349 * register value is read from the supplied execution context, so 350 * the result is valid only if the execution context is about to 351 * execute the branch in question. Invalid if not an indirect 352 * branch (i.e. isIndirectCtrl() should be true). 353 */ 354 virtual Addr branchTarget(ExecContext *xc) const 355 { 356 panic("StaticInst::branchTarget() called on instruction " 357 "that is not an indirect branch."); 358 } 359 360 /** 361 * Return true if the instruction is a control transfer, and if so, 362 * return the target address as well. 363 */ 364 bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const; 365 366 /** 367 * Return string representation of disassembled instruction. 368 * The default version of this function will call the internal 369 * virtual generateDisassembly() function to get the string, 370 * then cache it in #cachedDisassembly. If the disassembly 371 * should not be cached, this function should be overridden directly. 372 */ 373 virtual const std::string &disassemble(Addr pc, 374 const SymbolTable *symtab = 0) const 375 { 376 if (!cachedDisassembly) 377 cachedDisassembly = 378 new std::string(generateDisassembly(pc, symtab)); 379 380 return *cachedDisassembly; 381 } 382 383 /// Decoded instruction cache type. 384 /// For now we're using a generic hash_map; this seems to work 385 /// pretty well. 386 typedef m5::hash_map<MachInst, StaticInstPtr<ISA> > DecodeCache; 387 388 /// A cache of decoded instruction objects. 389 static DecodeCache decodeCache; 390 391 /** 392 * Dump some basic stats on the decode cache hash map. 393 * Only gets called if DECODE_CACHE_HASH_STATS is defined. 394 */ 395 static void dumpDecodeCacheStats(); 396 397 /// Decode a machine instruction. 398 /// @param mach_inst The binary instruction to decode. 399 /// @retval A pointer to the corresponding StaticInst object. 400 static 401 StaticInstPtr<ISA> decode(MachInst mach_inst) 402 { 403#ifdef DECODE_CACHE_HASH_STATS 404 // Simple stats on decode hash_map. Turns out the default 405 // hash function is as good as anything I could come up with. 406 const int dump_every_n = 10000000; 407 static int decodes_til_dump = dump_every_n; 408 409 if (--decodes_til_dump == 0) { 410 dumpDecodeCacheStats(); 411 decodes_til_dump = dump_every_n; 412 } 413#endif 414 415 typename DecodeCache::iterator iter = decodeCache.find(mach_inst); 416 if (iter != decodeCache.end()) { 417 return iter->second; 418 } 419 420 StaticInstPtr<ISA> si = ISA::decodeInst(mach_inst); 421 decodeCache[mach_inst] = si; 422 return si; 423 } 424}; 425 426typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr; 427 428/// Reference-counted pointer to a StaticInst object. 429/// This type should be used instead of "StaticInst<ISA> *" so that 430/// StaticInst objects can be properly reference-counted. 431template <class ISA> 432class StaticInstPtr : public RefCountingPtr<StaticInst<ISA> > 433{ 434 public: 435 /// Constructor. 436 StaticInstPtr() 437 : RefCountingPtr<StaticInst<ISA> >() 438 { 439 } 440 441 /// Conversion from "StaticInst<ISA> *". 442 StaticInstPtr(StaticInst<ISA> *p) 443 : RefCountingPtr<StaticInst<ISA> >(p) 444 { 445 } 446 447 /// Copy constructor. 448 StaticInstPtr(const StaticInstPtr &r) 449 : RefCountingPtr<StaticInst<ISA> >(r) 450 { 451 } 452 453 /// Construct directly from machine instruction. 454 /// Calls StaticInst<ISA>::decode(). 455 StaticInstPtr(typename ISA::MachInst mach_inst) 456 : RefCountingPtr<StaticInst<ISA> >(StaticInst<ISA>::decode(mach_inst)) 457 { 458 } 459 460 /// Convert to pointer to StaticInstBase class. 461 operator const StaticInstBasePtr() 462 { 463 return this->get(); 464 } 465}; 466 467#endif // __STATIC_INST_HH__ 468