static_inst.hh revision 12614:0bc465e1f5fb
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * Authors: Steve Reinhardt 30 */ 31 32#ifndef __CPU_STATIC_INST_HH__ 33#define __CPU_STATIC_INST_HH__ 34 35#include <bitset> 36#include <memory> 37#include <string> 38 39#include "arch/registers.hh" 40#include "arch/types.hh" 41#include "base/logging.hh" 42#include "base/refcnt.hh" 43#include "base/types.hh" 44#include "config/the_isa.hh" 45#include "cpu/op_class.hh" 46#include "cpu/reg_class.hh" 47#include "cpu/reg_class_impl.hh" 48#include "cpu/static_inst_fwd.hh" 49#include "cpu/thread_context.hh" 50#include "enums/StaticInstFlags.hh" 51#include "sim/byteswap.hh" 52 53// forward declarations 54class Packet; 55 56class ExecContext; 57 58class SymbolTable; 59 60namespace Trace { 61 class InstRecord; 62} 63 64/** 65 * Base, ISA-independent static instruction class. 66 * 67 * The main component of this class is the vector of flags and the 68 * associated methods for reading them. Any object that can rely 69 * solely on these flags can process instructions without being 70 * recompiled for multiple ISAs. 71 */ 72class StaticInst : public RefCounted, public StaticInstFlags 73{ 74 public: 75 /// Binary extended machine instruction type. 76 typedef TheISA::ExtMachInst ExtMachInst; 77 78 enum { 79 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 80 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs 81 }; 82 83 protected: 84 85 /// Flag values for this instruction. 86 std::bitset<Num_Flags> flags; 87 88 /// See opClass(). 89 OpClass _opClass; 90 91 /// See numSrcRegs(). 92 int8_t _numSrcRegs; 93 94 /// See numDestRegs(). 95 int8_t _numDestRegs; 96 97 /// The following are used to track physical register usage 98 /// for machines with separate int & FP reg files. 99 //@{ 100 int8_t _numFPDestRegs; 101 int8_t _numIntDestRegs; 102 int8_t _numCCDestRegs; 103 //@} 104 105 /** To use in architectures with vector register file. */ 106 /** @{ */ 107 int8_t _numVecDestRegs; 108 int8_t _numVecElemDestRegs; 109 /** @} */ 110 111 public: 112 113 /// @name Register information. 114 /// The sum of numFPDestRegs(), numIntDestRegs(), numVecDestRegs() and 115 /// numVecelemDestRegs() equals numDestRegs(). The former two functions 116 /// are used to track physical register usage for machines with separate 117 /// int & FP reg files, the next two is for machines with vector register 118 /// file. 119 //@{ 120 /// Number of source registers. 121 int8_t numSrcRegs() const { return _numSrcRegs; } 122 /// Number of destination registers. 123 int8_t numDestRegs() const { return _numDestRegs; } 124 /// Number of floating-point destination regs. 125 int8_t numFPDestRegs() const { return _numFPDestRegs; } 126 /// Number of integer destination regs. 127 int8_t numIntDestRegs() const { return _numIntDestRegs; } 128 /// Number of vector destination regs. 129 int8_t numVecDestRegs() const { return _numVecDestRegs; } 130 /// Number of vector element destination regs. 131 int8_t numVecElemDestRegs() const { return _numVecElemDestRegs; } 132 /// Number of coprocesor destination regs. 133 int8_t numCCDestRegs() const { return _numCCDestRegs; } 134 //@} 135 136 /// @name Flag accessors. 137 /// These functions are used to access the values of the various 138 /// instruction property flags. See StaticInst::Flags for descriptions 139 /// of the individual flags. 140 //@{ 141 142 bool isNop() const { return flags[IsNop]; } 143 144 bool isMemRef() const { return flags[IsMemRef]; } 145 bool isLoad() const { return flags[IsLoad]; } 146 bool isStore() const { return flags[IsStore]; } 147 bool isStoreConditional() const { return flags[IsStoreConditional]; } 148 bool isInstPrefetch() const { return flags[IsInstPrefetch]; } 149 bool isDataPrefetch() const { return flags[IsDataPrefetch]; } 150 bool isPrefetch() const { return isInstPrefetch() || 151 isDataPrefetch(); } 152 153 bool isInteger() const { return flags[IsInteger]; } 154 bool isFloating() const { return flags[IsFloating]; } 155 bool isVector() const { return flags[IsVector]; } 156 bool isCC() const { return flags[IsCC]; } 157 158 bool isControl() const { return flags[IsControl]; } 159 bool isCall() const { return flags[IsCall]; } 160 bool isReturn() const { return flags[IsReturn]; } 161 bool isDirectCtrl() const { return flags[IsDirectControl]; } 162 bool isIndirectCtrl() const { return flags[IsIndirectControl]; } 163 bool isCondCtrl() const { return flags[IsCondControl]; } 164 bool isUncondCtrl() const { return flags[IsUncondControl]; } 165 bool isCondDelaySlot() const { return flags[IsCondDelaySlot]; } 166 167 bool isThreadSync() const { return flags[IsThreadSync]; } 168 bool isSerializing() const { return flags[IsSerializing] || 169 flags[IsSerializeBefore] || 170 flags[IsSerializeAfter]; } 171 bool isSerializeBefore() const { return flags[IsSerializeBefore]; } 172 bool isSerializeAfter() const { return flags[IsSerializeAfter]; } 173 bool isSquashAfter() const { return flags[IsSquashAfter]; } 174 bool isMemBarrier() const { return flags[IsMemBarrier]; } 175 bool isWriteBarrier() const { return flags[IsWriteBarrier]; } 176 bool isNonSpeculative() const { return flags[IsNonSpeculative]; } 177 bool isQuiesce() const { return flags[IsQuiesce]; } 178 bool isIprAccess() const { return flags[IsIprAccess]; } 179 bool isUnverifiable() const { return flags[IsUnverifiable]; } 180 bool isSyscall() const { return flags[IsSyscall]; } 181 bool isMacroop() const { return flags[IsMacroop]; } 182 bool isMicroop() const { return flags[IsMicroop]; } 183 bool isDelayedCommit() const { return flags[IsDelayedCommit]; } 184 bool isLastMicroop() const { return flags[IsLastMicroop]; } 185 bool isFirstMicroop() const { return flags[IsFirstMicroop]; } 186 //This flag doesn't do anything yet 187 bool isMicroBranch() const { return flags[IsMicroBranch]; } 188 //@} 189 190 void setFirstMicroop() { flags[IsFirstMicroop] = true; } 191 void setLastMicroop() { flags[IsLastMicroop] = true; } 192 void setDelayedCommit() { flags[IsDelayedCommit] = true; } 193 void setFlag(Flags f) { flags[f] = true; } 194 195 /// Operation class. Used to select appropriate function unit in issue. 196 OpClass opClass() const { return _opClass; } 197 198 199 /// Return logical index (architectural reg num) of i'th destination reg. 200 /// Only the entries from 0 through numDestRegs()-1 are valid. 201 const RegId& destRegIdx(int i) const { return _destRegIdx[i]; } 202 203 /// Return logical index (architectural reg num) of i'th source reg. 204 /// Only the entries from 0 through numSrcRegs()-1 are valid. 205 const RegId& srcRegIdx(int i) const { return _srcRegIdx[i]; } 206 207 /// Pointer to a statically allocated "null" instruction object. 208 static StaticInstPtr nullStaticInstPtr; 209 210 /// Pointer to a statically allocated generic "nop" instruction object. 211 static StaticInstPtr nopStaticInstPtr; 212 213 /// The binary machine instruction. 214 const ExtMachInst machInst; 215 216 protected: 217 218 /// See destRegIdx(). 219 RegId _destRegIdx[MaxInstDestRegs]; 220 /// See srcRegIdx(). 221 RegId _srcRegIdx[MaxInstSrcRegs]; 222 223 /** 224 * Base mnemonic (e.g., "add"). Used by generateDisassembly() 225 * methods. Also useful to readily identify instructions from 226 * within the debugger when #cachedDisassembly has not been 227 * initialized. 228 */ 229 const char *mnemonic; 230 231 /** 232 * String representation of disassembly (lazily evaluated via 233 * disassemble()). 234 */ 235 mutable std::string *cachedDisassembly; 236 237 /** 238 * Internal function to generate disassembly string. 239 */ 240 virtual std::string 241 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0; 242 243 /// Constructor. 244 /// It's important to initialize everything here to a sane 245 /// default, since the decoder generally only overrides 246 /// the fields that are meaningful for the particular 247 /// instruction. 248 StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass) 249 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0), 250 _numFPDestRegs(0), _numIntDestRegs(0), _numCCDestRegs(0), 251 _numVecDestRegs(0), _numVecElemDestRegs(0), machInst(_machInst), 252 mnemonic(_mnemonic), cachedDisassembly(0) 253 { } 254 255 public: 256 virtual ~StaticInst(); 257 258 virtual Fault execute(ExecContext *xc, 259 Trace::InstRecord *traceData) const = 0; 260 261 virtual Fault initiateAcc(ExecContext *xc, 262 Trace::InstRecord *traceData) const 263 { 264 panic("initiateAcc not defined!"); 265 } 266 267 virtual Fault completeAcc(Packet *pkt, ExecContext *xc, 268 Trace::InstRecord *traceData) const 269 { 270 panic("completeAcc not defined!"); 271 } 272 273 virtual void advancePC(TheISA::PCState &pcState) const = 0; 274 275 /** 276 * Return the microop that goes with a particular micropc. This should 277 * only be defined/used in macroops which will contain microops 278 */ 279 virtual StaticInstPtr fetchMicroop(MicroPC upc) const; 280 281 /** 282 * Return the target address for a PC-relative branch. 283 * Invalid if not a PC-relative branch (i.e. isDirectCtrl() 284 * should be true). 285 */ 286 virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const; 287 288 /** 289 * Return the target address for an indirect branch (jump). The 290 * register value is read from the supplied thread context, so 291 * the result is valid only if the thread context is about to 292 * execute the branch in question. Invalid if not an indirect 293 * branch (i.e. isIndirectCtrl() should be true). 294 */ 295 virtual TheISA::PCState branchTarget(ThreadContext *tc) const; 296 297 /** 298 * Return true if the instruction is a control transfer, and if so, 299 * return the target address as well. 300 */ 301 bool hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc, 302 TheISA::PCState &tgt) const; 303 304 /** 305 * Return string representation of disassembled instruction. 306 * The default version of this function will call the internal 307 * virtual generateDisassembly() function to get the string, 308 * then cache it in #cachedDisassembly. If the disassembly 309 * should not be cached, this function should be overridden directly. 310 */ 311 virtual const std::string &disassemble(Addr pc, 312 const SymbolTable *symtab = 0) const; 313 314 /** 315 * Print a separator separated list of this instruction's set flag 316 * names on the given stream. 317 */ 318 void printFlags(std::ostream &outs, const std::string &separator) const; 319 320 /// Return name of machine instruction 321 std::string getName() { return mnemonic; } 322 323 protected: 324 template<typename T> 325 size_t 326 simpleAsBytes(void *buf, size_t max_size, const T &t) 327 { 328 size_t size = sizeof(T); 329 if (size <= max_size) 330 *reinterpret_cast<T *>(buf) = htole<T>(t); 331 return size; 332 } 333 334 public: 335 /** 336 * Instruction classes can override this function to return a 337 * a representation of themselves as a blob of bytes, generally assumed to 338 * be that instructions ExtMachInst. 339 * 340 * buf is a buffer to hold the bytes. 341 * max_size is the size allocated for that buffer by the caller. 342 * The return value is how much data was actually put into the buffer, 343 * zero if no data was put in the buffer, or the necessary size of the 344 * buffer if there wasn't enough space. 345 */ 346 virtual size_t asBytes(void *buf, size_t max_size) { return 0; } 347}; 348 349#endif // __CPU_STATIC_INST_HH__ 350