static_inst.hh revision 593 
1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __STATIC_INST_HH__
30#define __STATIC_INST_HH__
31
32#include <bitset>
33#include <string>
34
35#include "sim/host.hh"
36#include "base/hashmap.hh"
37#include "base/refcnt.hh"
38
39#include "cpu/full_cpu/op_class.hh"
40#include "targetarch/isa_traits.hh"
41
42// forward declarations
43class ExecContext;
44class SpecExecContext;
45class SimpleCPU;
46class FullCPU;
47class DynInst;
48class SymbolTable;
49
50namespace Trace {
51    class InstRecord;
52}
53
54/**
55 * Base, ISA-independent static instruction class.
56 *
57 * The main component of this class is the vector of flags and the
58 * associated methods for reading them.  Any object that can rely
59 * solely on these flags can process instructions without being
60 * recompiled for multiple ISAs.
61 */
62class StaticInstBase : public RefCounted
63{
64  protected:
65
66    /// Set of boolean static instruction properties.
67    ///
68    /// Notes:
69    /// - The IsInteger and IsFloating flags are based on the class of
70    /// registers accessed by the instruction.  Although most
71    /// instructions will have exactly one of these two flags set, it
72    /// is possible for an instruction to have neither (e.g., direct
73    /// unconditional branches, memory barriers) or both (e.g., an
74    /// FP/int conversion).
75    /// - If IsMemRef is set, then exactly one of IsLoad or IsStore
76    /// will be set.  Prefetches are marked as IsLoad, even if they
77    /// prefetch exclusive copies.
78    /// - If IsControl is set, then exactly one of IsDirectControl or
79    /// IsIndirect Control will be set, and exactly one of
80    /// IsCondControl or IsUncondControl will be set.
81    /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are
82    /// implemented as flags since in the current model there's no
83    /// other way for instructions to inject behavior into the
84    /// pipeline outside of fetch.  Once we go to an exec-in-exec CPU
85    /// model we should be able to get rid of these flags and
86    /// implement this behavior via the execute() methods.
87    ///
88    enum Flags {
89        IsNop,		///< Is a no-op (no effect at all).
90
91        IsInteger,	///< References integer regs.
92        IsFloating,	///< References FP regs.
93
94        IsMemRef,	///< References memory (load, store, or prefetch).
95        IsLoad,		///< Reads from memory (load or prefetch).
96        IsStore,	///< Writes to memory.
97        IsInstPrefetch,	///< Instruction-cache prefetch.
98        IsDataPrefetch,	///< Data-cache prefetch.
99        IsCopy,         ///< Fast Cache block copy
100
101        IsControl,		///< Control transfer instruction.
102        IsDirectControl,	///< PC relative control transfer.
103        IsIndirectControl,	///< Register indirect control transfer.
104        IsCondControl,		///< Conditional control transfer.
105        IsUncondControl,	///< Unconditional control transfer.
106        IsCall,			///< Subroutine call.
107        IsReturn,		///< Subroutine return.
108
109        IsThreadSync,	///< Thread synchronization operation.
110
111        IsSerializing,	///< Serializes pipeline: won't until all
112                        /// older instructions have committed.
113        IsMemBarrier,	///< Is a memory barrier
114        IsWriteBarrier,	///< Is a write barrier
115
116        NumFlags
117    };
118
119    /// Flag values for this instruction.
120    std::bitset<NumFlags> flags;
121
122    /// See opClass().
123    OpClass _opClass;
124
125    /// See numSrcRegs().
126    int8_t _numSrcRegs;
127
128    /// See numDestRegs().
129    int8_t _numDestRegs;
130
131    /// The following are used to track physical register usage
132    /// for machines with separate int & FP reg files.
133    //@{
134    int8_t _numFPDestRegs;
135    int8_t _numIntDestRegs;
136    //@}
137
138    /// Constructor.
139    /// It's important to initialize everything here to a sane
140    /// default, since the decoder generally only overrides
141    /// the fields that are meaningful for the particular
142    /// instruction.
143    StaticInstBase(OpClass __opClass)
144        : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
145          _numFPDestRegs(0), _numIntDestRegs(0)
146    {
147    }
148
149  public:
150
151    /// @name Register information.
152    /// The sum of numFPDestRegs() and numIntDestRegs() equals
153    /// numDestRegs().  The former two functions are used to track
154    /// physical register usage for machines with separate int & FP
155    /// reg files.
156    //@{
157    /// Number of source registers.
158    int8_t numSrcRegs()  const { return _numSrcRegs; }
159    /// Number of destination registers.
160    int8_t numDestRegs() const { return _numDestRegs; }
161    /// Number of floating-point destination regs.
162    int8_t numFPDestRegs()  const { return _numFPDestRegs; }
163    /// Number of integer destination regs.
164    int8_t numIntDestRegs() const { return _numIntDestRegs; }
165    //@}
166
167    /// @name Flag accessors.
168    /// These functions are used to access the values of the various
169    /// instruction property flags.  See StaticInstBase::Flags for descriptions
170    /// of the individual flags.
171    //@{
172
173    bool isNop() 	  const { return flags[IsNop]; }
174
175    bool isMemRef()    	  const { return flags[IsMemRef]; }
176    bool isLoad()	  const { return flags[IsLoad]; }
177    bool isStore()	  const { return flags[IsStore]; }
178    bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
179    bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
180    bool isCopy()         const { return flags[IsCopy];}
181
182    bool isInteger()	  const { return flags[IsInteger]; }
183    bool isFloating()	  const { return flags[IsFloating]; }
184
185    bool isControl()	  const { return flags[IsControl]; }
186    bool isCall()	  const { return flags[IsCall]; }
187    bool isReturn()	  const { return flags[IsReturn]; }
188    bool isDirectCtrl()	  const { return flags[IsDirectControl]; }
189    bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
190    bool isCondCtrl()	  const { return flags[IsCondControl]; }
191    bool isUncondCtrl()	  const { return flags[IsUncondControl]; }
192
193    bool isThreadSync()   const { return flags[IsThreadSync]; }
194    bool isSerializing()  const { return flags[IsSerializing]; }
195    bool isMemBarrier()   const { return flags[IsMemBarrier]; }
196    bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
197    //@}
198
199    /// Operation class.  Used to select appropriate function unit in issue.
200    OpClass opClass()     const { return _opClass; }
201};
202
203
204// forward declaration
205template <class ISA>
206class StaticInstPtr;
207
208/**
209 * Generic yet ISA-dependent static instruction class.
210 *
211 * This class builds on StaticInstBase, defining fields and interfaces
212 * that are generic across all ISAs but that differ in details
213 * according to the specific ISA being used.
214 */
215template <class ISA>
216class StaticInst : public StaticInstBase
217{
218  public:
219
220    /// Binary machine instruction type.
221    typedef typename ISA::MachInst MachInst;
222    /// Memory address type.
223    typedef typename ISA::Addr	   Addr;
224    /// Logical register index type.
225    typedef typename ISA::RegIndex RegIndex;
226
227    enum {
228        MaxInstSrcRegs = ISA::MaxInstSrcRegs,	//< Max source regs
229        MaxInstDestRegs = ISA::MaxInstDestRegs,	//< Max dest regs
230    };
231
232
233    /// Return logical index (architectural reg num) of i'th destination reg.
234    /// Only the entries from 0 through numDestRegs()-1 are valid.
235    RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
236
237    /// Return logical index (architectural reg num) of i'th source reg.
238    /// Only the entries from 0 through numSrcRegs()-1 are valid.
239    RegIndex srcRegIdx(int i)  const { return _srcRegIdx[i]; }
240
241    /// Pointer to a statically allocated "null" instruction object.
242    /// Used to give eaCompInst() and memAccInst() something to return
243    /// when called on non-memory instructions.
244    static StaticInstPtr<ISA> nullStaticInstPtr;
245
246    /**
247     * Memory references only: returns "fake" instruction representing
248     * the effective address part of the memory operation.  Used to
249     * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
250     * just the EA computation.
251     */
252    virtual StaticInstPtr<ISA> eaCompInst() { return nullStaticInstPtr; }
253
254    /**
255     * Memory references only: returns "fake" instruction representing
256     * the memory access part of the memory operation.  Used to
257     * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
258     * just the memory access (not the EA computation).
259     */
260    virtual StaticInstPtr<ISA> memAccInst() { return nullStaticInstPtr; }
261
262    /// The binary machine instruction.
263    const MachInst machInst;
264
265  protected:
266
267    /// See destRegIdx().
268    RegIndex _destRegIdx[MaxInstDestRegs];
269    /// See srcRegIdx().
270    RegIndex _srcRegIdx[MaxInstSrcRegs];
271
272    /**
273     * Base mnemonic (e.g., "add").  Used by generateDisassembly()
274     * methods.  Also useful to readily identify instructions from
275     * within the debugger when #cachedDisassembly has not been
276     * initialized.
277     */
278    const char *mnemonic;
279
280    /**
281     * String representation of disassembly (lazily evaluated via
282     * disassemble()).
283     */
284    std::string *cachedDisassembly;
285
286    /**
287     * Internal function to generate disassembly string.
288     */
289    virtual std::string generateDisassembly(Addr pc,
290                                            const SymbolTable *symtab) = 0;
291
292    /// Constructor.
293    StaticInst(const char *_mnemonic, MachInst _machInst, OpClass __opClass)
294        : StaticInstBase(__opClass),
295          machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
296    {
297    }
298
299  public:
300
301    virtual ~StaticInst()
302    {
303        if (cachedDisassembly)
304            delete cachedDisassembly;
305    }
306
307    /**
308     * Execute this instruction under SimpleCPU model.
309     */
310    virtual Fault execute(SimpleCPU *cpu, ExecContext *xc,
311                          Trace::InstRecord *traceData) = 0;
312
313    /**
314     * Execute this instruction under detailed FullCPU model.
315     */
316    virtual Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
317                          Trace::InstRecord *traceData) = 0;
318
319    /**
320     * Return the target address for a PC-relative branch.
321     * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
322     * should be true).
323     */
324    virtual Addr branchTarget(Addr branchPC) const
325    {
326        panic("StaticInst::branchTarget() called on instruction "
327              "that is not a PC-relative branch.");
328    }
329
330    /**
331     * Return the target address for an indirect branch (jump).  The
332     * register value is read from the supplied execution context, so
333     * the result is valid only if the execution context is about to
334     * execute the branch in question.  Invalid if not an indirect
335     * branch (i.e. isIndirectCtrl() should be true).
336     */
337    virtual Addr branchTarget(ExecContext *xc) const
338    {
339        panic("StaticInst::branchTarget() called on instruction "
340              "that is not an indirect branch.");
341    }
342
343    /**
344     * Return true if the instruction is a control transfer, and if so,
345     * return the target address as well.
346     */
347    bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt);
348
349    /**
350     * Return string representation of disassembled instruction.
351     * The default version of this function will call the internal
352     * virtual generateDisassembly() function to get the string,
353     * then cache it in #cachedDisassembly.  If the disassembly
354     * should not be cached, this function should be overridden directly.
355     */
356    virtual const std::string &disassemble(Addr pc,
357                                           const SymbolTable *symtab = 0)
358    {
359        if (!cachedDisassembly)
360            cachedDisassembly =
361                new std::string(generateDisassembly(pc, symtab));
362
363        return *cachedDisassembly;
364    }
365
366    /// Decoded instruction cache type.
367    /// For now we're using a generic hash_map; this seems to work
368    /// pretty well.
369    typedef m5::hash_map<MachInst, StaticInstPtr<ISA> > DecodeCache;
370
371    /// A cache of decoded instruction objects.
372    static DecodeCache decodeCache;
373
374    /**
375     * Dump some basic stats on the decode cache hash map.
376     * Only gets called if DECODE_CACHE_HASH_STATS is defined.
377     */
378    static void dumpDecodeCacheStats();
379
380    /// Decode a machine instruction.
381    /// @param mach_inst The binary instruction to decode.
382    /// @retval A pointer to the corresponding StaticInst object.
383    static
384    StaticInstPtr<ISA> decode(MachInst mach_inst)
385    {
386#ifdef DECODE_CACHE_HASH_STATS
387        // Simple stats on decode hash_map.  Turns out the default
388        // hash function is as good as anything I could come up with.
389        const int dump_every_n = 10000000;
390        static int decodes_til_dump = dump_every_n;
391
392        if (--decodes_til_dump == 0) {
393            dumpDecodeCacheStats();
394            decodes_til_dump = dump_every_n;
395        }
396#endif
397
398        typename DecodeCache::iterator iter = decodeCache.find(mach_inst);
399        if (iter != decodeCache.end()) {
400            return iter->second;
401        }
402
403        StaticInstPtr<ISA> si = ISA::decodeInst(mach_inst);
404        decodeCache[mach_inst] = si;
405        return si;
406    }
407};
408
409typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
410
411/// Reference-counted pointer to a StaticInst object.
412/// This type should be used instead of "StaticInst<ISA> *" so that
413/// StaticInst objects can be properly reference-counted.
414template <class ISA>
415class StaticInstPtr : public RefCountingPtr<StaticInst<ISA> >
416{
417  public:
418    /// Constructor.
419    StaticInstPtr()
420        : RefCountingPtr<StaticInst<ISA> >()
421    {
422    }
423
424    /// Conversion from "StaticInst<ISA> *".
425    StaticInstPtr(StaticInst<ISA> *p)
426        : RefCountingPtr<StaticInst<ISA> >(p)
427    {
428    }
429
430    /// Copy constructor.
431    StaticInstPtr(const StaticInstPtr &r)
432        : RefCountingPtr<StaticInst<ISA> >(r)
433    {
434    }
435
436    /// Construct directly from machine instruction.
437    /// Calls StaticInst<ISA>::decode().
438    StaticInstPtr(typename ISA::MachInst mach_inst)
439        : RefCountingPtr<StaticInst<ISA> >(StaticInst<ISA>::decode(mach_inst))
440    {
441    }
442
443    /// Convert to pointer to StaticInstBase class.
444    operator const StaticInstBasePtr()
445    {
446        return get();
447    }
448};
449
450#endif // __STATIC_INST_HH__
451