static_inst.hh revision 2336
12623SN/A/* 22623SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu */ 282665Ssaidi@eecs.umich.edu 292623SN/A#ifndef __CPU_STATIC_INST_HH__ 302623SN/A#define __CPU_STATIC_INST_HH__ 312623SN/A 322623SN/A#include <bitset> 332623SN/A#include <string> 342623SN/A 352623SN/A#include "base/hashmap.hh" 362623SN/A#include "base/refcnt.hh" 372623SN/A#include "encumbered/cpu/full/op_class.hh" 382623SN/A#include "sim/host.hh" 392623SN/A#include "arch/isa_traits.hh" 402623SN/A 412623SN/A// forward declarations 422623SN/Astruct AlphaSimpleImpl; 432623SN/Astruct OzoneImpl; 442623SN/Astruct SimpleImpl; 452623SN/Aclass ExecContext; 462623SN/Aclass DynInst; 472623SN/A 482623SN/Atemplate <class Impl> 492623SN/Aclass AlphaDynInst; 502623SN/A 512623SN/Atemplate <class Impl> 522623SN/Aclass OzoneDynInst; 532623SN/A 542623SN/Aclass CheckerCPU; 552680Sktlim@umich.educlass FastCPU; 562680Sktlim@umich.educlass SimpleCPU; 572623SN/Aclass InorderCPU; 582623SN/Aclass SymbolTable; 592680Sktlim@umich.edu 602623SN/Anamespace Trace { 612623SN/A class InstRecord; 622623SN/A} 632623SN/A 642623SN/A/** 652630SN/A * Base, ISA-independent static instruction class. 662623SN/A * 672623SN/A * The main component of this class is the vector of flags and the 682623SN/A * associated methods for reading them. Any object that can rely 692623SN/A * solely on these flags can process instructions without being 702623SN/A * recompiled for multiple ISAs. 712623SN/A */ 722630SN/Aclass StaticInstBase : public RefCounted 732623SN/A{ 742623SN/A protected: 752623SN/A 762623SN/A /// Set of boolean static instruction properties. 772623SN/A /// 782623SN/A /// Notes: 792623SN/A /// - The IsInteger and IsFloating flags are based on the class of 802631SN/A /// registers accessed by the instruction. Although most 812631SN/A /// instructions will have exactly one of these two flags set, it 822631SN/A /// is possible for an instruction to have neither (e.g., direct 832623SN/A /// unconditional branches, memory barriers) or both (e.g., an 842623SN/A /// FP/int conversion). 852623SN/A /// - If IsMemRef is set, then exactly one of IsLoad or IsStore 862623SN/A /// will be set. 872623SN/A /// - If IsControl is set, then exactly one of IsDirectControl or 882623SN/A /// IsIndirect Control will be set, and exactly one of 892623SN/A /// IsCondControl or IsUncondControl will be set. 902623SN/A /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are 912839Sktlim@umich.edu /// implemented as flags since in the current model there's no 922798Sktlim@umich.edu /// other way for instructions to inject behavior into the 932623SN/A /// pipeline outside of fetch. Once we go to an exec-in-exec CPU 942623SN/A /// model we should be able to get rid of these flags and 952623SN/A /// implement this behavior via the execute() methods. 962623SN/A /// 972623SN/A enum Flags { 982623SN/A IsNop, ///< Is a no-op (no effect at all). 992623SN/A 1002623SN/A IsInteger, ///< References integer regs. 1012623SN/A IsFloating, ///< References FP regs. 1022623SN/A 1032798Sktlim@umich.edu IsMemRef, ///< References memory (load, store, or prefetch). 1042623SN/A IsLoad, ///< Reads from memory (load or prefetch). 1052623SN/A IsStore, ///< Writes to memory. 1062623SN/A IsStoreConditional, ///< Store conditional instruction. 1072623SN/A IsInstPrefetch, ///< Instruction-cache prefetch. 1082623SN/A IsDataPrefetch, ///< Data-cache prefetch. 1092623SN/A IsCopy, ///< Fast Cache block copy 1102798Sktlim@umich.edu 1112623SN/A IsControl, ///< Control transfer instruction. 1122798Sktlim@umich.edu IsDirectControl, ///< PC relative control transfer. 1132798Sktlim@umich.edu IsIndirectControl, ///< Register indirect control transfer. 1142798Sktlim@umich.edu IsCondControl, ///< Conditional control transfer. 1152839Sktlim@umich.edu IsUncondControl, ///< Unconditional control transfer. 1162798Sktlim@umich.edu IsCall, ///< Subroutine call. 1172839Sktlim@umich.edu IsReturn, ///< Subroutine return. 1182798Sktlim@umich.edu 1192798Sktlim@umich.edu IsCondDelaySlot,///< Conditional Delay-Slot Instruction 1202839Sktlim@umich.edu 1212798Sktlim@umich.edu IsThreadSync, ///< Thread synchronization operation. 1222798Sktlim@umich.edu 1232839Sktlim@umich.edu IsSerializing, ///< Serializes pipeline: won't execute until all 1242839Sktlim@umich.edu /// older instructions have committed. 1252798Sktlim@umich.edu IsSerializeBefore, 1262798Sktlim@umich.edu IsSerializeAfter, 1272623SN/A IsMemBarrier, ///< Is a memory barrier 1282623SN/A IsWriteBarrier, ///< Is a write barrier 1292623SN/A 1302798Sktlim@umich.edu IsNonSpeculative, ///< Should not be executed speculatively 1312623SN/A IsQuiesce, ///< Is a quiesce instruction 1322798Sktlim@umich.edu 1332798Sktlim@umich.edu IsIprAccess, ///< Accesses IPRs 1342798Sktlim@umich.edu IsUnverifiable, ///< Can't be verified by a checker 1352798Sktlim@umich.edu 1362623SN/A NumFlags 1372798Sktlim@umich.edu }; 1382798Sktlim@umich.edu 1392798Sktlim@umich.edu /// Flag values for this instruction. 1402798Sktlim@umich.edu std::bitset<NumFlags> flags; 1412798Sktlim@umich.edu 1422798Sktlim@umich.edu /// See opClass(). 1432798Sktlim@umich.edu OpClass _opClass; 1442798Sktlim@umich.edu 1452798Sktlim@umich.edu /// See numSrcRegs(). 1462798Sktlim@umich.edu int8_t _numSrcRegs; 1472798Sktlim@umich.edu 1482798Sktlim@umich.edu /// See numDestRegs(). 1492798Sktlim@umich.edu int8_t _numDestRegs; 1502623SN/A 1512623SN/A /// The following are used to track physical register usage 1522623SN/A /// for machines with separate int & FP reg files. 1532623SN/A //@{ 1542623SN/A int8_t _numFPDestRegs; 1552623SN/A int8_t _numIntDestRegs; 1562623SN/A //@} 1572623SN/A 1582680Sktlim@umich.edu /// Constructor. 1592623SN/A /// It's important to initialize everything here to a sane 1602680Sktlim@umich.edu /// default, since the decoder generally only overrides 1612680Sktlim@umich.edu /// the fields that are meaningful for the particular 1622680Sktlim@umich.edu /// instruction. 1632623SN/A StaticInstBase(OpClass __opClass) 1642623SN/A : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0), 1652623SN/A _numFPDestRegs(0), _numIntDestRegs(0) 1662623SN/A { 1672623SN/A } 1682623SN/A 1692623SN/A public: 1702623SN/A 1712623SN/A /// @name Register information. 1722623SN/A /// The sum of numFPDestRegs() and numIntDestRegs() equals 1732623SN/A /// numDestRegs(). The former two functions are used to track 1742683Sktlim@umich.edu /// physical register usage for machines with separate int & FP 1752623SN/A /// reg files. 1762623SN/A //@{ 1772623SN/A /// Number of source registers. 1782623SN/A int8_t numSrcRegs() const { return _numSrcRegs; } 1792623SN/A /// Number of destination registers. 1802623SN/A int8_t numDestRegs() const { return _numDestRegs; } 1812623SN/A /// Number of floating-point destination regs. 1822623SN/A int8_t numFPDestRegs() const { return _numFPDestRegs; } 1832623SN/A /// Number of integer destination regs. 1842623SN/A int8_t numIntDestRegs() const { return _numIntDestRegs; } 1852623SN/A //@} 1862623SN/A 1872623SN/A /// @name Flag accessors. 1882623SN/A /// These functions are used to access the values of the various 1892623SN/A /// instruction property flags. See StaticInstBase::Flags for descriptions 1902623SN/A /// of the individual flags. 1912683Sktlim@umich.edu //@{ 1922623SN/A 1932644Sstever@eecs.umich.edu bool isNop() const { return flags[IsNop]; } 1942623SN/A 1952644Sstever@eecs.umich.edu bool isMemRef() const { return flags[IsMemRef]; } 1962644Sstever@eecs.umich.edu bool isLoad() const { return flags[IsLoad]; } 1972623SN/A bool isStore() const { return flags[IsStore]; } 1982623SN/A bool isStoreConditional() const { return flags[IsStoreConditional]; } 1992623SN/A bool isInstPrefetch() const { return flags[IsInstPrefetch]; } 2002623SN/A bool isDataPrefetch() const { return flags[IsDataPrefetch]; } 2012623SN/A bool isCopy() const { return flags[IsCopy];} 2022623SN/A 2032623SN/A bool isInteger() const { return flags[IsInteger]; } 2042623SN/A bool isFloating() const { return flags[IsFloating]; } 2052623SN/A 2062623SN/A bool isControl() const { return flags[IsControl]; } 2072663Sstever@eecs.umich.edu bool isCall() const { return flags[IsCall]; } 2082663Sstever@eecs.umich.edu bool isReturn() const { return flags[IsReturn]; } 2092835Srdreslin@umich.edu bool isDirectCtrl() const { return flags[IsDirectControl]; } 2102683Sktlim@umich.edu bool isIndirectCtrl() const { return flags[IsIndirectControl]; } 2112623SN/A bool isCondCtrl() const { return flags[IsCondControl]; } 2122623SN/A bool isUncondCtrl() const { return flags[IsUncondControl]; } 2132623SN/A 2142623SN/A bool isThreadSync() const { return flags[IsThreadSync]; } 2152623SN/A bool isSerializing() const { return flags[IsSerializing] || 2162623SN/A flags[IsSerializeBefore] || 2172683Sktlim@umich.edu flags[IsSerializeAfter]; } 2182623SN/A bool isSerializeBefore() const { return flags[IsSerializeBefore]; } 2192623SN/A bool isSerializeAfter() const { return flags[IsSerializeAfter]; } 2202623SN/A bool isMemBarrier() const { return flags[IsMemBarrier]; } 2212641Sstever@eecs.umich.edu bool isWriteBarrier() const { return flags[IsWriteBarrier]; } 2222641Sstever@eecs.umich.edu bool isNonSpeculative() const { return flags[IsNonSpeculative]; } 2232623SN/A bool isQuiesce() const { return flags[IsQuiesce]; } 2242623SN/A bool isIprAccess() const { return flags[IsIprAccess]; } 2252630SN/A bool isUnverifiable() const { return flags[IsUnverifiable]; } 2262623SN/A //@} 2272623SN/A 2282623SN/A /// Operation class. Used to select appropriate function unit in issue. 2292623SN/A OpClass opClass() const { return _opClass; } 2302623SN/A}; 2312623SN/A 2322623SN/A 2332623SN/A// forward declaration 2342623SN/Aclass StaticInstPtr; 2352623SN/A 2362623SN/A/** 2372623SN/A * Generic yet ISA-dependent static instruction class. 2382623SN/A * 2392623SN/A * This class builds on StaticInstBase, defining fields and interfaces 2402623SN/A * that are generic across all ISAs but that differ in details 2412623SN/A * according to the specific ISA being used. 2422623SN/A */ 2432623SN/Aclass StaticInst : public StaticInstBase 2442623SN/A{ 2452623SN/A public: 2462623SN/A 2472623SN/A /// Binary machine instruction type. 2482623SN/A typedef TheISA::MachInst MachInst; 2492623SN/A /// Binary extended machine instruction type. 2502623SN/A typedef TheISA::ExtMachInst ExtMachInst; 2512623SN/A /// Logical register index type. 2522623SN/A typedef TheISA::RegIndex RegIndex; 2532623SN/A 2542623SN/A enum { 2552623SN/A MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 2562623SN/A MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs 2572623SN/A }; 2582623SN/A 2592623SN/A 2602623SN/A /// Return logical index (architectural reg num) of i'th destination reg. 2612623SN/A /// Only the entries from 0 through numDestRegs()-1 are valid. 2622623SN/A RegIndex destRegIdx(int i) const { return _destRegIdx[i]; } 2632623SN/A 2642623SN/A /// Return logical index (architectural reg num) of i'th source reg. 2652623SN/A /// Only the entries from 0 through numSrcRegs()-1 are valid. 2662623SN/A RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; } 2672623SN/A 2682623SN/A /// Pointer to a statically allocated "null" instruction object. 2692623SN/A /// Used to give eaCompInst() and memAccInst() something to return 2702623SN/A /// when called on non-memory instructions. 2712623SN/A static StaticInstPtr nullStaticInstPtr; 2722623SN/A 2732623SN/A /** 2742623SN/A * Memory references only: returns "fake" instruction representing 2752623SN/A * the effective address part of the memory operation. Used to 2762623SN/A * obtain the dependence info (numSrcRegs and srcRegIdx[]) for 2772623SN/A * just the EA computation. 2782623SN/A */ 2792623SN/A virtual const 2802623SN/A StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; } 2812623SN/A 2822623SN/A /** 2832623SN/A * Memory references only: returns "fake" instruction representing 2842623SN/A * the memory access part of the memory operation. Used to 2852623SN/A * obtain the dependence info (numSrcRegs and srcRegIdx[]) for 2862623SN/A * just the memory access (not the EA computation). 2872623SN/A */ 2882663Sstever@eecs.umich.edu virtual const 2892663Sstever@eecs.umich.edu StaticInstPtr &memAccInst() const { return nullStaticInstPtr; } 2902835Srdreslin@umich.edu 2912683Sktlim@umich.edu /// The binary machine instruction. 2922623SN/A const ExtMachInst machInst; 2932623SN/A 2942683Sktlim@umich.edu protected: 2952623SN/A 2962623SN/A /// See destRegIdx(). 2972641Sstever@eecs.umich.edu RegIndex _destRegIdx[MaxInstDestRegs]; 2982641Sstever@eecs.umich.edu /// See srcRegIdx(). 2992623SN/A RegIndex _srcRegIdx[MaxInstSrcRegs]; 3002623SN/A 3012623SN/A /** 3022630SN/A * Base mnemonic (e.g., "add"). Used by generateDisassembly() 3032623SN/A * methods. Also useful to readily identify instructions from 3042623SN/A * within the debugger when #cachedDisassembly has not been 3052623SN/A * initialized. 3062623SN/A */ 3072623SN/A const char *mnemonic; 3082623SN/A 3092623SN/A /** 3102623SN/A * String representation of disassembly (lazily evaluated via 3112623SN/A * disassemble()). 3122623SN/A */ 3132623SN/A mutable std::string *cachedDisassembly; 3142623SN/A 3152623SN/A /** 3162623SN/A * Internal function to generate disassembly string. 3172623SN/A */ 3182623SN/A virtual std::string 3192623SN/A generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0; 3202623SN/A 3212623SN/A /// Constructor. 3222623SN/A StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass) 3232623SN/A : StaticInstBase(__opClass), 3242623SN/A machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0) 3252623SN/A { 3262623SN/A } 3272623SN/A 3282623SN/A public: 3292623SN/A 3302623SN/A virtual ~StaticInst() 3312623SN/A { 3322623SN/A if (cachedDisassembly) 3332623SN/A delete cachedDisassembly; 3342623SN/A } 3352623SN/A 3362623SN/A/** 3372623SN/A * The execute() signatures are auto-generated by scons based on the 3382623SN/A * set of CPU models we are compiling in today. 3392623SN/A */ 3402623SN/A#include "cpu/static_inst_exec_sigs.hh" 3412623SN/A 3422623SN/A /** 3432623SN/A * Return the target address for a PC-relative branch. 3442623SN/A * Invalid if not a PC-relative branch (i.e. isDirectCtrl() 3452623SN/A * should be true). 3462623SN/A */ 3472623SN/A virtual Addr branchTarget(Addr branchPC) const 3482623SN/A { 3492623SN/A panic("StaticInst::branchTarget() called on instruction " 3502623SN/A "that is not a PC-relative branch."); 3512623SN/A } 3522623SN/A 3532623SN/A /** 3542623SN/A * Return the target address for an indirect branch (jump). The 3552623SN/A * register value is read from the supplied execution context, so 3562623SN/A * the result is valid only if the execution context is about to 3572623SN/A * execute the branch in question. Invalid if not an indirect 3582623SN/A * branch (i.e. isIndirectCtrl() should be true). 3592623SN/A */ 3602623SN/A virtual Addr branchTarget(ExecContext *xc) const 3612623SN/A { 3622623SN/A panic("StaticInst::branchTarget() called on instruction " 3632623SN/A "that is not an indirect branch."); 3642623SN/A } 3652623SN/A 3662623SN/A /** 3672623SN/A * Return true if the instruction is a control transfer, and if so, 3682623SN/A * return the target address as well. 3692623SN/A */ 3702631SN/A bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const; 3712631SN/A 3722663Sstever@eecs.umich.edu /** 3732663Sstever@eecs.umich.edu * Return string representation of disassembled instruction. 3742835Srdreslin@umich.edu * The default version of this function will call the internal 3752662Sstever@eecs.umich.edu * virtual generateDisassembly() function to get the string, 3762623SN/A * then cache it in #cachedDisassembly. If the disassembly 3772641Sstever@eecs.umich.edu * should not be cached, this function should be overridden directly. 3782623SN/A */ 3792623SN/A virtual const std::string &disassemble(Addr pc, 3802623SN/A const SymbolTable *symtab = 0) const 3812630SN/A { 3822623SN/A if (!cachedDisassembly) 3832623SN/A cachedDisassembly = 3842623SN/A new std::string(generateDisassembly(pc, symtab)); 3852623SN/A 3862623SN/A return *cachedDisassembly; 3872623SN/A } 3882623SN/A 3892623SN/A /// Decoded instruction cache type. 3902623SN/A /// For now we're using a generic hash_map; this seems to work 3912644Sstever@eecs.umich.edu /// pretty well. 3922644Sstever@eecs.umich.edu typedef m5::hash_map<ExtMachInst, StaticInstPtr> DecodeCache; 3932623SN/A 3942623SN/A /// A cache of decoded instruction objects. 3952623SN/A static DecodeCache decodeCache; 3962623SN/A 3972623SN/A /** 3982644Sstever@eecs.umich.edu * Dump some basic stats on the decode cache hash map. 3992623SN/A * Only gets called if DECODE_CACHE_HASH_STATS is defined. 4002623SN/A */ 4012623SN/A static void dumpDecodeCacheStats(); 4022631SN/A 4032631SN/A /// Decode a machine instruction. 4042631SN/A /// @param mach_inst The binary instruction to decode. 4052631SN/A /// @retval A pointer to the corresponding StaticInst object. 4062631SN/A //This is defined as inline below. 4072631SN/A static StaticInstPtr decode(ExtMachInst mach_inst); 4082623SN/A}; 4092623SN/A 4102623SN/Atypedef RefCountingPtr<StaticInstBase> StaticInstBasePtr; 4112623SN/A 4122644Sstever@eecs.umich.edu/// Reference-counted pointer to a StaticInst object. 4132623SN/A/// This type should be used instead of "StaticInst *" so that 4142623SN/A/// StaticInst objects can be properly reference-counted. 4152623SN/Aclass StaticInstPtr : public RefCountingPtr<StaticInst> 4162644Sstever@eecs.umich.edu{ 4172623SN/A public: 4182798Sktlim@umich.edu /// Constructor. 4192623SN/A StaticInstPtr() 4202644Sstever@eecs.umich.edu : RefCountingPtr<StaticInst>() 4212644Sstever@eecs.umich.edu { 4222644Sstever@eecs.umich.edu } 4232644Sstever@eecs.umich.edu 4242839Sktlim@umich.edu /// Conversion from "StaticInst *". 4252839Sktlim@umich.edu StaticInstPtr(StaticInst *p) 4262798Sktlim@umich.edu : RefCountingPtr<StaticInst>(p) 4272798Sktlim@umich.edu { 4282798Sktlim@umich.edu } 4292623SN/A 4302644Sstever@eecs.umich.edu /// Copy constructor. 4312623SN/A StaticInstPtr(const StaticInstPtr &r) 4322623SN/A : RefCountingPtr<StaticInst>(r) 4332644Sstever@eecs.umich.edu { 4342644Sstever@eecs.umich.edu } 4352644Sstever@eecs.umich.edu 4362644Sstever@eecs.umich.edu /// Construct directly from machine instruction. 4372644Sstever@eecs.umich.edu /// Calls StaticInst::decode(). 4382644Sstever@eecs.umich.edu StaticInstPtr(TheISA::ExtMachInst mach_inst) 4392644Sstever@eecs.umich.edu : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst)) 4402644Sstever@eecs.umich.edu { 4412644Sstever@eecs.umich.edu } 4422623SN/A 4432623SN/A /// Convert to pointer to StaticInstBase class. 4442623SN/A operator const StaticInstBasePtr() 4452644Sstever@eecs.umich.edu { 4462644Sstever@eecs.umich.edu return this->get(); 4472623SN/A } 4482623SN/A}; 4492623SN/A 4502623SN/Ainline StaticInstPtr 4512623SN/AStaticInst::decode(StaticInst::ExtMachInst mach_inst) 4522630SN/A{ 4532623SN/A#ifdef DECODE_CACHE_HASH_STATS 4542855Srdreslin@umich.edu // Simple stats on decode hash_map. Turns out the default 4552855Srdreslin@umich.edu // hash function is as good as anything I could come up with. 4562855Srdreslin@umich.edu const int dump_every_n = 10000000; 4572855Srdreslin@umich.edu static int decodes_til_dump = dump_every_n; 4582855Srdreslin@umich.edu 4592855Srdreslin@umich.edu if (--decodes_til_dump == 0) { 4602623SN/A dumpDecodeCacheStats(); 4612623SN/A decodes_til_dump = dump_every_n; 4622623SN/A } 4632657Ssaidi@eecs.umich.edu#endif 4642623SN/A 4652623SN/A DecodeCache::iterator iter = decodeCache.find(mach_inst); 4662623SN/A if (iter != decodeCache.end()) { 4672623SN/A return iter->second; 4682623SN/A } 4692623SN/A 4702623SN/A StaticInstPtr si = TheISA::decodeInst(mach_inst); 4712657Ssaidi@eecs.umich.edu decodeCache[mach_inst] = si; 4722657Ssaidi@eecs.umich.edu return si; 4732657Ssaidi@eecs.umich.edu} 4742657Ssaidi@eecs.umich.edu 4752623SN/A#endif // __CPU_STATIC_INST_HH__ 4762623SN/A