static_inst.hh revision 2155 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __CPU_STATIC_INST_HH__
30#define __CPU_STATIC_INST_HH__
31
32#include <bitset>
33#include <string>
34
35#include "base/hashmap.hh"
36#include "base/refcnt.hh"
37#include "encumbered/cpu/full/op_class.hh"
38#include "sim/host.hh"
39#include "arch/isa_traits.hh"
40
41// forward declarations
42struct AlphaSimpleImpl;
43class ExecContext;
44class DynInst;
45
46template <class Impl>
47class AlphaDynInst;
48
49class FastCPU;
50class SimpleCPU;
51class InorderCPU;
52class SymbolTable;
53
54namespace Trace {
55    class InstRecord;
56}
57
58/**
59 * Base, ISA-independent static instruction class.
60 *
61 * The main component of this class is the vector of flags and the
62 * associated methods for reading them.  Any object that can rely
63 * solely on these flags can process instructions without being
64 * recompiled for multiple ISAs.
65 */
66class StaticInstBase : public RefCounted
67{
68  protected:
69
70    /// Set of boolean static instruction properties.
71    ///
72    /// Notes:
73    /// - The IsInteger and IsFloating flags are based on the class of
74    /// registers accessed by the instruction.  Although most
75    /// instructions will have exactly one of these two flags set, it
76    /// is possible for an instruction to have neither (e.g., direct
77    /// unconditional branches, memory barriers) or both (e.g., an
78    /// FP/int conversion).
79    /// - If IsMemRef is set, then exactly one of IsLoad or IsStore
80    /// will be set.
81    /// - If IsControl is set, then exactly one of IsDirectControl or
82    /// IsIndirect Control will be set, and exactly one of
83    /// IsCondControl or IsUncondControl will be set.
84    /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are
85    /// implemented as flags since in the current model there's no
86    /// other way for instructions to inject behavior into the
87    /// pipeline outside of fetch.  Once we go to an exec-in-exec CPU
88    /// model we should be able to get rid of these flags and
89    /// implement this behavior via the execute() methods.
90    ///
91    enum Flags {
92        IsNop,		///< Is a no-op (no effect at all).
93
94        IsInteger,	///< References integer regs.
95        IsFloating,	///< References FP regs.
96
97        IsMemRef,	///< References memory (load, store, or prefetch).
98        IsLoad,		///< Reads from memory (load or prefetch).
99        IsStore,	///< Writes to memory.
100        IsInstPrefetch,	///< Instruction-cache prefetch.
101        IsDataPrefetch,	///< Data-cache prefetch.
102        IsCopy,         ///< Fast Cache block copy
103
104        IsControl,		///< Control transfer instruction.
105        IsDirectControl,	///< PC relative control transfer.
106        IsIndirectControl,	///< Register indirect control transfer.
107        IsCondControl,		///< Conditional control transfer.
108        IsUncondControl,	///< Unconditional control transfer.
109        IsCall,			///< Subroutine call.
110        IsReturn,		///< Subroutine return.
111
112        IsThreadSync,	///< Thread synchronization operation.
113
114        IsSerializing,	///< Serializes pipeline: won't execute until all
115                        /// older instructions have committed.
116        IsSerializeBefore,
117        IsSerializeAfter,
118        IsMemBarrier,	///< Is a memory barrier
119        IsWriteBarrier,	///< Is a write barrier
120
121        IsNonSpeculative, ///< Should not be executed speculatively
122
123        NumFlags
124    };
125
126    /// Flag values for this instruction.
127    std::bitset<NumFlags> flags;
128
129    /// See opClass().
130    OpClass _opClass;
131
132    /// See numSrcRegs().
133    int8_t _numSrcRegs;
134
135    /// See numDestRegs().
136    int8_t _numDestRegs;
137
138    /// The following are used to track physical register usage
139    /// for machines with separate int & FP reg files.
140    //@{
141    int8_t _numFPDestRegs;
142    int8_t _numIntDestRegs;
143    //@}
144
145    /// Constructor.
146    /// It's important to initialize everything here to a sane
147    /// default, since the decoder generally only overrides
148    /// the fields that are meaningful for the particular
149    /// instruction.
150    StaticInstBase(OpClass __opClass)
151        : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
152          _numFPDestRegs(0), _numIntDestRegs(0)
153    {
154    }
155
156  public:
157
158    /// @name Register information.
159    /// The sum of numFPDestRegs() and numIntDestRegs() equals
160    /// numDestRegs().  The former two functions are used to track
161    /// physical register usage for machines with separate int & FP
162    /// reg files.
163    //@{
164    /// Number of source registers.
165    int8_t numSrcRegs()  const { return _numSrcRegs; }
166    /// Number of destination registers.
167    int8_t numDestRegs() const { return _numDestRegs; }
168    /// Number of floating-point destination regs.
169    int8_t numFPDestRegs()  const { return _numFPDestRegs; }
170    /// Number of integer destination regs.
171    int8_t numIntDestRegs() const { return _numIntDestRegs; }
172    //@}
173
174    /// @name Flag accessors.
175    /// These functions are used to access the values of the various
176    /// instruction property flags.  See StaticInstBase::Flags for descriptions
177    /// of the individual flags.
178    //@{
179
180    bool isNop() 	  const { return flags[IsNop]; }
181
182    bool isMemRef()    	  const { return flags[IsMemRef]; }
183    bool isLoad()	  const { return flags[IsLoad]; }
184    bool isStore()	  const { return flags[IsStore]; }
185    bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
186    bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
187    bool isCopy()         const { return flags[IsCopy];}
188
189    bool isInteger()	  const { return flags[IsInteger]; }
190    bool isFloating()	  const { return flags[IsFloating]; }
191
192    bool isControl()	  const { return flags[IsControl]; }
193    bool isCall()	  const { return flags[IsCall]; }
194    bool isReturn()	  const { return flags[IsReturn]; }
195    bool isDirectCtrl()	  const { return flags[IsDirectControl]; }
196    bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
197    bool isCondCtrl()	  const { return flags[IsCondControl]; }
198    bool isUncondCtrl()	  const { return flags[IsUncondControl]; }
199
200    bool isThreadSync()   const { return flags[IsThreadSync]; }
201    bool isSerializing()  const { return flags[IsSerializing] ||
202                                      flags[IsSerializeBefore] ||
203                                      flags[IsSerializeAfter]; }
204    bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
205    bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
206    bool isMemBarrier()   const { return flags[IsMemBarrier]; }
207    bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
208    bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
209    //@}
210
211    /// Operation class.  Used to select appropriate function unit in issue.
212    OpClass opClass()     const { return _opClass; }
213};
214
215
216// forward declaration
217class StaticInstPtr;
218
219/**
220 * Generic yet ISA-dependent static instruction class.
221 *
222 * This class builds on StaticInstBase, defining fields and interfaces
223 * that are generic across all ISAs but that differ in details
224 * according to the specific ISA being used.
225 */
226class StaticInst : public StaticInstBase
227{
228  public:
229
230    /// Binary machine instruction type.
231    typedef TheISA::MachInst MachInst;
232    /// Logical register index type.
233    typedef TheISA::RegIndex RegIndex;
234
235    enum {
236        MaxInstSrcRegs = TheISA::MaxInstSrcRegs,	//< Max source regs
237        MaxInstDestRegs = TheISA::MaxInstDestRegs,	//< Max dest regs
238    };
239
240
241    /// Return logical index (architectural reg num) of i'th destination reg.
242    /// Only the entries from 0 through numDestRegs()-1 are valid.
243    RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
244
245    /// Return logical index (architectural reg num) of i'th source reg.
246    /// Only the entries from 0 through numSrcRegs()-1 are valid.
247    RegIndex srcRegIdx(int i)  const { return _srcRegIdx[i]; }
248
249    /// Pointer to a statically allocated "null" instruction object.
250    /// Used to give eaCompInst() and memAccInst() something to return
251    /// when called on non-memory instructions.
252    static StaticInstPtr nullStaticInstPtr;
253
254    /**
255     * Memory references only: returns "fake" instruction representing
256     * the effective address part of the memory operation.  Used to
257     * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
258     * just the EA computation.
259     */
260    virtual const
261    StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; }
262
263    /**
264     * Memory references only: returns "fake" instruction representing
265     * the memory access part of the memory operation.  Used to
266     * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
267     * just the memory access (not the EA computation).
268     */
269    virtual const
270    StaticInstPtr &memAccInst() const { return nullStaticInstPtr; }
271
272    /// The binary machine instruction.
273    const MachInst machInst;
274
275  protected:
276
277    /// See destRegIdx().
278    RegIndex _destRegIdx[MaxInstDestRegs];
279    /// See srcRegIdx().
280    RegIndex _srcRegIdx[MaxInstSrcRegs];
281
282    /**
283     * Base mnemonic (e.g., "add").  Used by generateDisassembly()
284     * methods.  Also useful to readily identify instructions from
285     * within the debugger when #cachedDisassembly has not been
286     * initialized.
287     */
288    const char *mnemonic;
289
290    /**
291     * String representation of disassembly (lazily evaluated via
292     * disassemble()).
293     */
294    mutable std::string *cachedDisassembly;
295
296    /**
297     * Internal function to generate disassembly string.
298     */
299    virtual std::string
300    generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
301
302    /// Constructor.
303    StaticInst(const char *_mnemonic, MachInst _machInst, OpClass __opClass)
304        : StaticInstBase(__opClass),
305          machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
306    {
307    }
308
309  public:
310
311    virtual ~StaticInst()
312    {
313        if (cachedDisassembly)
314            delete cachedDisassembly;
315    }
316
317/**
318 * The execute() signatures are auto-generated by scons based on the
319 * set of CPU models we are compiling in today.
320 */
321#include "cpu/static_inst_exec_sigs.hh"
322
323    /**
324     * Return the target address for a PC-relative branch.
325     * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
326     * should be true).
327     */
328    virtual Addr branchTarget(Addr branchPC) const
329    {
330        panic("StaticInst::branchTarget() called on instruction "
331              "that is not a PC-relative branch.");
332    }
333
334    /**
335     * Return the target address for an indirect branch (jump).  The
336     * register value is read from the supplied execution context, so
337     * the result is valid only if the execution context is about to
338     * execute the branch in question.  Invalid if not an indirect
339     * branch (i.e. isIndirectCtrl() should be true).
340     */
341    virtual Addr branchTarget(ExecContext *xc) const
342    {
343        panic("StaticInst::branchTarget() called on instruction "
344              "that is not an indirect branch.");
345    }
346
347    /**
348     * Return true if the instruction is a control transfer, and if so,
349     * return the target address as well.
350     */
351    bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const;
352
353    /**
354     * Return string representation of disassembled instruction.
355     * The default version of this function will call the internal
356     * virtual generateDisassembly() function to get the string,
357     * then cache it in #cachedDisassembly.  If the disassembly
358     * should not be cached, this function should be overridden directly.
359     */
360    virtual const std::string &disassemble(Addr pc,
361                                           const SymbolTable *symtab = 0) const
362    {
363        if (!cachedDisassembly)
364            cachedDisassembly =
365                new std::string(generateDisassembly(pc, symtab));
366
367        return *cachedDisassembly;
368    }
369
370    /// Decoded instruction cache type.
371    /// For now we're using a generic hash_map; this seems to work
372    /// pretty well.
373    typedef m5::hash_map<MachInst, StaticInstPtr> DecodeCache;
374
375    /// A cache of decoded instruction objects.
376    static DecodeCache decodeCache;
377
378    /**
379     * Dump some basic stats on the decode cache hash map.
380     * Only gets called if DECODE_CACHE_HASH_STATS is defined.
381     */
382    static void dumpDecodeCacheStats();
383
384    /// Decode a machine instruction.
385    /// @param mach_inst The binary instruction to decode.
386    /// @retval A pointer to the corresponding StaticInst object.
387    //This is defined as inline below.
388    static StaticInstPtr decode(MachInst mach_inst);
389};
390
391typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
392
393/// Reference-counted pointer to a StaticInst object.
394/// This type should be used instead of "StaticInst *" so that
395/// StaticInst objects can be properly reference-counted.
396class StaticInstPtr : public RefCountingPtr<StaticInst>
397{
398  public:
399    /// Constructor.
400    StaticInstPtr()
401        : RefCountingPtr<StaticInst>()
402    {
403    }
404
405    /// Conversion from "StaticInst *".
406    StaticInstPtr(StaticInst *p)
407        : RefCountingPtr<StaticInst>(p)
408    {
409    }
410
411    /// Copy constructor.
412    StaticInstPtr(const StaticInstPtr &r)
413        : RefCountingPtr<StaticInst>(r)
414    {
415    }
416
417    /// Construct directly from machine instruction.
418    /// Calls StaticInst::decode().
419    StaticInstPtr(TheISA::MachInst mach_inst)
420        : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst))
421    {
422    }
423
424    /// Convert to pointer to StaticInstBase class.
425    operator const StaticInstBasePtr()
426    {
427        return this->get();
428    }
429};
430
431inline StaticInstPtr
432StaticInst::decode(StaticInst::MachInst mach_inst)
433{
434#ifdef DECODE_CACHE_HASH_STATS
435    // Simple stats on decode hash_map.  Turns out the default
436    // hash function is as good as anything I could come up with.
437    const int dump_every_n = 10000000;
438    static int decodes_til_dump = dump_every_n;
439
440    if (--decodes_til_dump == 0) {
441        dumpDecodeCacheStats();
442        decodes_til_dump = dump_every_n;
443    }
444#endif
445
446    DecodeCache::iterator iter = decodeCache.find(mach_inst);
447    if (iter != decodeCache.end()) {
448        return iter->second;
449    }
450
451    StaticInstPtr si = TheISA::decodeInst(mach_inst);
452    decodeCache[mach_inst] = si;
453    return si;
454}
455
456#endif // __CPU_STATIC_INST_HH__
457