static_inst.hh revision 2135
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __CPU_STATIC_INST_HH__ 30#define __CPU_STATIC_INST_HH__ 31 32#include <bitset> 33#include <string> 34 35#include "base/hashmap.hh" 36#include "base/refcnt.hh" 37#include "encumbered/cpu/full/op_class.hh" 38#include "sim/host.hh" 39#include "arch/isa_traits.hh" 40 41// forward declarations 42struct AlphaSimpleImpl; 43class ExecContext; 44class DynInst; 45 46template <class Impl> 47class AlphaDynInst; 48 49class FastCPU; 50class SimpleCPU; 51class InorderCPU; 52class SymbolTable; 53 54namespace Trace { 55 class InstRecord; 56} 57 58/** 59 * Base, ISA-independent static instruction class. 60 * 61 * The main component of this class is the vector of flags and the 62 * associated methods for reading them. Any object that can rely 63 * solely on these flags can process instructions without being 64 * recompiled for multiple ISAs. 65 */ 66class StaticInstBase : public RefCounted 67{ 68 protected: 69 70 /// Set of boolean static instruction properties. 71 /// 72 /// Notes: 73 /// - The IsInteger and IsFloating flags are based on the class of 74 /// registers accessed by the instruction. Although most 75 /// instructions will have exactly one of these two flags set, it 76 /// is possible for an instruction to have neither (e.g., direct 77 /// unconditional branches, memory barriers) or both (e.g., an 78 /// FP/int conversion). 79 /// - If IsMemRef is set, then exactly one of IsLoad or IsStore 80 /// will be set. 81 /// - If IsControl is set, then exactly one of IsDirectControl or 82 /// IsIndirect Control will be set, and exactly one of 83 /// IsCondControl or IsUncondControl will be set. 84 /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are 85 /// implemented as flags since in the current model there's no 86 /// other way for instructions to inject behavior into the 87 /// pipeline outside of fetch. Once we go to an exec-in-exec CPU 88 /// model we should be able to get rid of these flags and 89 /// implement this behavior via the execute() methods. 90 /// 91 enum Flags { 92 IsNop, ///< Is a no-op (no effect at all). 93 94 IsInteger, ///< References integer regs. 95 IsFloating, ///< References FP regs. 96 97 IsMemRef, ///< References memory (load, store, or prefetch). 98 IsLoad, ///< Reads from memory (load or prefetch). 99 IsStore, ///< Writes to memory. 100 IsInstPrefetch, ///< Instruction-cache prefetch. 101 IsDataPrefetch, ///< Data-cache prefetch. 102 IsCopy, ///< Fast Cache block copy 103 104 IsControl, ///< Control transfer instruction. 105 IsDirectControl, ///< PC relative control transfer. 106 IsIndirectControl, ///< Register indirect control transfer. 107 IsCondControl, ///< Conditional control transfer. 108 IsUncondControl, ///< Unconditional control transfer. 109 IsCall, ///< Subroutine call. 110 IsReturn, ///< Subroutine return. 111 112 IsCondDelaySlot,///< Conditional Delay-Slot Instruction 113 114 IsThreadSync, ///< Thread synchronization operation. 115 116 IsSerializing, ///< Serializes pipeline: won't execute until all 117 /// older instructions have committed. 118 IsSerializeBefore, 119 IsSerializeAfter, 120 IsMemBarrier, ///< Is a memory barrier 121 IsWriteBarrier, ///< Is a write barrier 122 123 IsNonSpeculative, ///< Should not be executed speculatively 124 125 NumFlags 126 }; 127 128 /// Flag values for this instruction. 129 std::bitset<NumFlags> flags; 130 131 /// See opClass(). 132 OpClass _opClass; 133 134 /// See numSrcRegs(). 135 int8_t _numSrcRegs; 136 137 /// See numDestRegs(). 138 int8_t _numDestRegs; 139 140 /// The following are used to track physical register usage 141 /// for machines with separate int & FP reg files. 142 //@{ 143 int8_t _numFPDestRegs; 144 int8_t _numIntDestRegs; 145 //@} 146 147 /// Constructor. 148 /// It's important to initialize everything here to a sane 149 /// default, since the decoder generally only overrides 150 /// the fields that are meaningful for the particular 151 /// instruction. 152 StaticInstBase(OpClass __opClass) 153 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0), 154 _numFPDestRegs(0), _numIntDestRegs(0) 155 { 156 } 157 158 public: 159 160 /// @name Register information. 161 /// The sum of numFPDestRegs() and numIntDestRegs() equals 162 /// numDestRegs(). The former two functions are used to track 163 /// physical register usage for machines with separate int & FP 164 /// reg files. 165 //@{ 166 /// Number of source registers. 167 int8_t numSrcRegs() const { return _numSrcRegs; } 168 /// Number of destination registers. 169 int8_t numDestRegs() const { return _numDestRegs; } 170 /// Number of floating-point destination regs. 171 int8_t numFPDestRegs() const { return _numFPDestRegs; } 172 /// Number of integer destination regs. 173 int8_t numIntDestRegs() const { return _numIntDestRegs; } 174 //@} 175 176 /// @name Flag accessors. 177 /// These functions are used to access the values of the various 178 /// instruction property flags. See StaticInstBase::Flags for descriptions 179 /// of the individual flags. 180 //@{ 181 182 bool isNop() const { return flags[IsNop]; } 183 184 bool isMemRef() const { return flags[IsMemRef]; } 185 bool isLoad() const { return flags[IsLoad]; } 186 bool isStore() const { return flags[IsStore]; } 187 bool isInstPrefetch() const { return flags[IsInstPrefetch]; } 188 bool isDataPrefetch() const { return flags[IsDataPrefetch]; } 189 bool isCopy() const { return flags[IsCopy];} 190 191 bool isInteger() const { return flags[IsInteger]; } 192 bool isFloating() const { return flags[IsFloating]; } 193 194 bool isControl() const { return flags[IsControl]; } 195 bool isCall() const { return flags[IsCall]; } 196 bool isReturn() const { return flags[IsReturn]; } 197 bool isDirectCtrl() const { return flags[IsDirectControl]; } 198 bool isIndirectCtrl() const { return flags[IsIndirectControl]; } 199 bool isCondCtrl() const { return flags[IsCondControl]; } 200 bool isUncondCtrl() const { return flags[IsUncondControl]; } 201 202 bool isThreadSync() const { return flags[IsThreadSync]; } 203 bool isSerializing() const { return flags[IsSerializing] || 204 flags[IsSerializeBefore] || 205 flags[IsSerializeAfter]; } 206 bool isSerializeBefore() const { return flags[IsSerializeBefore]; } 207 bool isSerializeAfter() const { return flags[IsSerializeAfter]; } 208 bool isMemBarrier() const { return flags[IsMemBarrier]; } 209 bool isWriteBarrier() const { return flags[IsWriteBarrier]; } 210 bool isNonSpeculative() const { return flags[IsNonSpeculative]; } 211 //@} 212 213 /// Operation class. Used to select appropriate function unit in issue. 214 OpClass opClass() const { return _opClass; } 215}; 216 217 218// forward declaration 219class StaticInstPtr; 220 221/** 222 * Generic yet ISA-dependent static instruction class. 223 * 224 * This class builds on StaticInstBase, defining fields and interfaces 225 * that are generic across all ISAs but that differ in details 226 * according to the specific ISA being used. 227 */ 228class StaticInst : public StaticInstBase 229{ 230 public: 231 232 /// Binary machine instruction type. 233 typedef TheISA::MachInst MachInst; 234 /// Logical register index type. 235 typedef TheISA::RegIndex RegIndex; 236 237 enum { 238 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 239 MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs 240 }; 241 242 243 /// Return logical index (architectural reg num) of i'th destination reg. 244 /// Only the entries from 0 through numDestRegs()-1 are valid. 245 RegIndex destRegIdx(int i) const { return _destRegIdx[i]; } 246 247 /// Return logical index (architectural reg num) of i'th source reg. 248 /// Only the entries from 0 through numSrcRegs()-1 are valid. 249 RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; } 250 251 /// Pointer to a statically allocated "null" instruction object. 252 /// Used to give eaCompInst() and memAccInst() something to return 253 /// when called on non-memory instructions. 254 static StaticInstPtr nullStaticInstPtr; 255 256 /** 257 * Memory references only: returns "fake" instruction representing 258 * the effective address part of the memory operation. Used to 259 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for 260 * just the EA computation. 261 */ 262 virtual const 263 StaticInstPtr &eaCompInst() const { return nullStaticInstPtr; } 264 265 /** 266 * Memory references only: returns "fake" instruction representing 267 * the memory access part of the memory operation. Used to 268 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for 269 * just the memory access (not the EA computation). 270 */ 271 virtual const 272 StaticInstPtr &memAccInst() const { return nullStaticInstPtr; } 273 274 /// The binary machine instruction. 275 const MachInst machInst; 276 277 protected: 278 279 /// See destRegIdx(). 280 RegIndex _destRegIdx[MaxInstDestRegs]; 281 /// See srcRegIdx(). 282 RegIndex _srcRegIdx[MaxInstSrcRegs]; 283 284 /** 285 * Base mnemonic (e.g., "add"). Used by generateDisassembly() 286 * methods. Also useful to readily identify instructions from 287 * within the debugger when #cachedDisassembly has not been 288 * initialized. 289 */ 290 const char *mnemonic; 291 292 /** 293 * String representation of disassembly (lazily evaluated via 294 * disassemble()). 295 */ 296 mutable std::string *cachedDisassembly; 297 298 /** 299 * Internal function to generate disassembly string. 300 */ 301 virtual std::string 302 generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0; 303 304 /// Constructor. 305 StaticInst(const char *_mnemonic, MachInst _machInst, OpClass __opClass) 306 : StaticInstBase(__opClass), 307 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0) 308 { 309 } 310 311 public: 312 313 virtual ~StaticInst() 314 { 315 if (cachedDisassembly) 316 delete cachedDisassembly; 317 } 318 319#include "static_inst_impl.hh" 320 321 /** 322 * Return the target address for a PC-relative branch. 323 * Invalid if not a PC-relative branch (i.e. isDirectCtrl() 324 * should be true). 325 */ 326 virtual Addr branchTarget(Addr branchPC) const 327 { 328 panic("StaticInst::branchTarget() called on instruction " 329 "that is not a PC-relative branch."); 330 } 331 332 /** 333 * Return the target address for an indirect branch (jump). The 334 * register value is read from the supplied execution context, so 335 * the result is valid only if the execution context is about to 336 * execute the branch in question. Invalid if not an indirect 337 * branch (i.e. isIndirectCtrl() should be true). 338 */ 339 virtual Addr branchTarget(ExecContext *xc) const 340 { 341 panic("StaticInst::branchTarget() called on instruction " 342 "that is not an indirect branch."); 343 } 344 345 /** 346 * Return true if the instruction is a control transfer, and if so, 347 * return the target address as well. 348 */ 349 bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const; 350 351 /** 352 * Return string representation of disassembled instruction. 353 * The default version of this function will call the internal 354 * virtual generateDisassembly() function to get the string, 355 * then cache it in #cachedDisassembly. If the disassembly 356 * should not be cached, this function should be overridden directly. 357 */ 358 virtual const std::string &disassemble(Addr pc, 359 const SymbolTable *symtab = 0) const 360 { 361 if (!cachedDisassembly) 362 cachedDisassembly = 363 new std::string(generateDisassembly(pc, symtab)); 364 365 return *cachedDisassembly; 366 } 367 368 /// Decoded instruction cache type. 369 /// For now we're using a generic hash_map; this seems to work 370 /// pretty well. 371 typedef m5::hash_map<MachInst, StaticInstPtr> DecodeCache; 372 373 /// A cache of decoded instruction objects. 374 static DecodeCache decodeCache; 375 376 /** 377 * Dump some basic stats on the decode cache hash map. 378 * Only gets called if DECODE_CACHE_HASH_STATS is defined. 379 */ 380 static void dumpDecodeCacheStats(); 381 382 /// Decode a machine instruction. 383 /// @param mach_inst The binary instruction to decode. 384 /// @retval A pointer to the corresponding StaticInst object. 385 //This is defined as inline below. 386 static StaticInstPtr decode(MachInst mach_inst); 387}; 388 389typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr; 390 391/// Reference-counted pointer to a StaticInst object. 392/// This type should be used instead of "StaticInst *" so that 393/// StaticInst objects can be properly reference-counted. 394class StaticInstPtr : public RefCountingPtr<StaticInst> 395{ 396 public: 397 /// Constructor. 398 StaticInstPtr() 399 : RefCountingPtr<StaticInst>() 400 { 401 } 402 403 /// Conversion from "StaticInst *". 404 StaticInstPtr(StaticInst *p) 405 : RefCountingPtr<StaticInst>(p) 406 { 407 } 408 409 /// Copy constructor. 410 StaticInstPtr(const StaticInstPtr &r) 411 : RefCountingPtr<StaticInst>(r) 412 { 413 } 414 415 /// Construct directly from machine instruction. 416 /// Calls StaticInst::decode(). 417 StaticInstPtr(TheISA::MachInst mach_inst) 418 : RefCountingPtr<StaticInst>(StaticInst::decode(mach_inst)) 419 { 420 } 421 422 /// Convert to pointer to StaticInstBase class. 423 operator const StaticInstBasePtr() 424 { 425 return this->get(); 426 } 427}; 428 429inline StaticInstPtr 430StaticInst::decode(StaticInst::MachInst mach_inst) 431{ 432#ifdef DECODE_CACHE_HASH_STATS 433 // Simple stats on decode hash_map. Turns out the default 434 // hash function is as good as anything I could come up with. 435 const int dump_every_n = 10000000; 436 static int decodes_til_dump = dump_every_n; 437 438 if (--decodes_til_dump == 0) { 439 dumpDecodeCacheStats(); 440 decodes_til_dump = dump_every_n; 441 } 442#endif 443 444 DecodeCache::iterator iter = decodeCache.find(mach_inst); 445 if (iter != decodeCache.end()) { 446 return iter->second; 447 } 448 449 StaticInstPtr si = TheISA::decodeInst(mach_inst); 450 decodeCache[mach_inst] = si; 451 return si; 452} 453 454#endif // __CPU_STATIC_INST_HH__ 455