static_inst.hh revision 1681 
1/*
2 * Copyright (c) 2003-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __CPU_STATIC_INST_HH__
30#define __CPU_STATIC_INST_HH__
31
32#include <bitset>
33#include <string>
34
35#include "sim/host.hh"
36#include "base/hashmap.hh"
37#include "base/refcnt.hh"
38
39#include "cpu/full_cpu/op_class.hh"
40#include "targetarch/isa_traits.hh"
41
42// forward declarations
43struct AlphaSimpleImpl;
44class ExecContext;
45class DynInst;
46
47template <class Impl>
48class AlphaDynInst;
49
50class FastCPU;
51class SimpleCPU;
52class InorderCPU;
53class SymbolTable;
54
55namespace Trace {
56    class InstRecord;
57}
58
59/**
60 * Base, ISA-independent static instruction class.
61 *
62 * The main component of this class is the vector of flags and the
63 * associated methods for reading them.  Any object that can rely
64 * solely on these flags can process instructions without being
65 * recompiled for multiple ISAs.
66 */
67class StaticInstBase : public RefCounted
68{
69  protected:
70
71    /// Set of boolean static instruction properties.
72    ///
73    /// Notes:
74    /// - The IsInteger and IsFloating flags are based on the class of
75    /// registers accessed by the instruction.  Although most
76    /// instructions will have exactly one of these two flags set, it
77    /// is possible for an instruction to have neither (e.g., direct
78    /// unconditional branches, memory barriers) or both (e.g., an
79    /// FP/int conversion).
80    /// - If IsMemRef is set, then exactly one of IsLoad or IsStore
81    /// will be set.
82    /// - If IsControl is set, then exactly one of IsDirectControl or
83    /// IsIndirect Control will be set, and exactly one of
84    /// IsCondControl or IsUncondControl will be set.
85    /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are
86    /// implemented as flags since in the current model there's no
87    /// other way for instructions to inject behavior into the
88    /// pipeline outside of fetch.  Once we go to an exec-in-exec CPU
89    /// model we should be able to get rid of these flags and
90    /// implement this behavior via the execute() methods.
91    ///
92    enum Flags {
93        IsNop,		///< Is a no-op (no effect at all).
94
95        IsInteger,	///< References integer regs.
96        IsFloating,	///< References FP regs.
97
98        IsMemRef,	///< References memory (load, store, or prefetch).
99        IsLoad,		///< Reads from memory (load or prefetch).
100        IsStore,	///< Writes to memory.
101        IsInstPrefetch,	///< Instruction-cache prefetch.
102        IsDataPrefetch,	///< Data-cache prefetch.
103        IsCopy,         ///< Fast Cache block copy
104
105        IsControl,		///< Control transfer instruction.
106        IsDirectControl,	///< PC relative control transfer.
107        IsIndirectControl,	///< Register indirect control transfer.
108        IsCondControl,		///< Conditional control transfer.
109        IsUncondControl,	///< Unconditional control transfer.
110        IsCall,			///< Subroutine call.
111        IsReturn,		///< Subroutine return.
112
113        IsThreadSync,	///< Thread synchronization operation.
114
115        IsSerializing,	///< Serializes pipeline: won't execute until all
116                        /// older instructions have committed.
117        IsMemBarrier,	///< Is a memory barrier
118        IsWriteBarrier,	///< Is a write barrier
119
120        IsNonSpeculative, ///< Should not be executed speculatively
121
122        NumFlags
123    };
124
125    /// Flag values for this instruction.
126    std::bitset<NumFlags> flags;
127
128    /// See opClass().
129    OpClass _opClass;
130
131    /// See numSrcRegs().
132    int8_t _numSrcRegs;
133
134    /// See numDestRegs().
135    int8_t _numDestRegs;
136
137    /// The following are used to track physical register usage
138    /// for machines with separate int & FP reg files.
139    //@{
140    int8_t _numFPDestRegs;
141    int8_t _numIntDestRegs;
142    //@}
143
144    /// Constructor.
145    /// It's important to initialize everything here to a sane
146    /// default, since the decoder generally only overrides
147    /// the fields that are meaningful for the particular
148    /// instruction.
149    StaticInstBase(OpClass __opClass)
150        : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
151          _numFPDestRegs(0), _numIntDestRegs(0)
152    {
153    }
154
155  public:
156
157    /// @name Register information.
158    /// The sum of numFPDestRegs() and numIntDestRegs() equals
159    /// numDestRegs().  The former two functions are used to track
160    /// physical register usage for machines with separate int & FP
161    /// reg files.
162    //@{
163    /// Number of source registers.
164    int8_t numSrcRegs()  const { return _numSrcRegs; }
165    /// Number of destination registers.
166    int8_t numDestRegs() const { return _numDestRegs; }
167    /// Number of floating-point destination regs.
168    int8_t numFPDestRegs()  const { return _numFPDestRegs; }
169    /// Number of integer destination regs.
170    int8_t numIntDestRegs() const { return _numIntDestRegs; }
171    //@}
172
173    /// @name Flag accessors.
174    /// These functions are used to access the values of the various
175    /// instruction property flags.  See StaticInstBase::Flags for descriptions
176    /// of the individual flags.
177    //@{
178
179    bool isNop() 	  const { return flags[IsNop]; }
180
181    bool isMemRef()    	  const { return flags[IsMemRef]; }
182    bool isLoad()	  const { return flags[IsLoad]; }
183    bool isStore()	  const { return flags[IsStore]; }
184    bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
185    bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
186    bool isCopy()         const { return flags[IsCopy];}
187
188    bool isInteger()	  const { return flags[IsInteger]; }
189    bool isFloating()	  const { return flags[IsFloating]; }
190
191    bool isControl()	  const { return flags[IsControl]; }
192    bool isCall()	  const { return flags[IsCall]; }
193    bool isReturn()	  const { return flags[IsReturn]; }
194    bool isDirectCtrl()	  const { return flags[IsDirectControl]; }
195    bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
196    bool isCondCtrl()	  const { return flags[IsCondControl]; }
197    bool isUncondCtrl()	  const { return flags[IsUncondControl]; }
198
199    bool isThreadSync()   const { return flags[IsThreadSync]; }
200    bool isSerializing()  const { return flags[IsSerializing]; }
201    bool isMemBarrier()   const { return flags[IsMemBarrier]; }
202    bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
203    bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
204    //@}
205
206    /// Operation class.  Used to select appropriate function unit in issue.
207    OpClass opClass()     const { return _opClass; }
208};
209
210
211// forward declaration
212template <class ISA>
213class StaticInstPtr;
214
215/**
216 * Generic yet ISA-dependent static instruction class.
217 *
218 * This class builds on StaticInstBase, defining fields and interfaces
219 * that are generic across all ISAs but that differ in details
220 * according to the specific ISA being used.
221 */
222template <class ISA>
223class StaticInst : public StaticInstBase
224{
225  public:
226
227    /// Binary machine instruction type.
228    typedef typename ISA::MachInst MachInst;
229    /// Memory address type.
230    typedef typename ISA::Addr	   Addr;
231    /// Logical register index type.
232    typedef typename ISA::RegIndex RegIndex;
233
234    enum {
235        MaxInstSrcRegs = ISA::MaxInstSrcRegs,	//< Max source regs
236        MaxInstDestRegs = ISA::MaxInstDestRegs,	//< Max dest regs
237    };
238
239
240    /// Return logical index (architectural reg num) of i'th destination reg.
241    /// Only the entries from 0 through numDestRegs()-1 are valid.
242    RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
243
244    /// Return logical index (architectural reg num) of i'th source reg.
245    /// Only the entries from 0 through numSrcRegs()-1 are valid.
246    RegIndex srcRegIdx(int i)  const { return _srcRegIdx[i]; }
247
248    /// Pointer to a statically allocated "null" instruction object.
249    /// Used to give eaCompInst() and memAccInst() something to return
250    /// when called on non-memory instructions.
251    static StaticInstPtr<ISA> nullStaticInstPtr;
252
253    /**
254     * Memory references only: returns "fake" instruction representing
255     * the effective address part of the memory operation.  Used to
256     * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
257     * just the EA computation.
258     */
259    virtual const
260    StaticInstPtr<ISA> &eaCompInst() const { return nullStaticInstPtr; }
261
262    /**
263     * Memory references only: returns "fake" instruction representing
264     * the memory access part of the memory operation.  Used to
265     * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
266     * just the memory access (not the EA computation).
267     */
268    virtual const
269    StaticInstPtr<ISA> &memAccInst() const { return nullStaticInstPtr; }
270
271    /// The binary machine instruction.
272    const MachInst machInst;
273
274  protected:
275
276    /// See destRegIdx().
277    RegIndex _destRegIdx[MaxInstDestRegs];
278    /// See srcRegIdx().
279    RegIndex _srcRegIdx[MaxInstSrcRegs];
280
281    /**
282     * Base mnemonic (e.g., "add").  Used by generateDisassembly()
283     * methods.  Also useful to readily identify instructions from
284     * within the debugger when #cachedDisassembly has not been
285     * initialized.
286     */
287    const char *mnemonic;
288
289    /**
290     * String representation of disassembly (lazily evaluated via
291     * disassemble()).
292     */
293    mutable std::string *cachedDisassembly;
294
295    /**
296     * Internal function to generate disassembly string.
297     */
298    virtual std::string
299    generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
300
301    /// Constructor.
302    StaticInst(const char *_mnemonic, MachInst _machInst, OpClass __opClass)
303        : StaticInstBase(__opClass),
304          machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
305    {
306    }
307
308  public:
309
310    virtual ~StaticInst()
311    {
312        if (cachedDisassembly)
313            delete cachedDisassembly;
314    }
315
316#include "static_inst_impl.hh"
317
318    /**
319     * Return the target address for a PC-relative branch.
320     * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
321     * should be true).
322     */
323    virtual Addr branchTarget(Addr branchPC) const
324    {
325        panic("StaticInst::branchTarget() called on instruction "
326              "that is not a PC-relative branch.");
327    }
328
329    /**
330     * Return the target address for an indirect branch (jump).  The
331     * register value is read from the supplied execution context, so
332     * the result is valid only if the execution context is about to
333     * execute the branch in question.  Invalid if not an indirect
334     * branch (i.e. isIndirectCtrl() should be true).
335     */
336    virtual Addr branchTarget(ExecContext *xc) const
337    {
338        panic("StaticInst::branchTarget() called on instruction "
339              "that is not an indirect branch.");
340    }
341
342    /**
343     * Return true if the instruction is a control transfer, and if so,
344     * return the target address as well.
345     */
346    bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const;
347
348    /**
349     * Return string representation of disassembled instruction.
350     * The default version of this function will call the internal
351     * virtual generateDisassembly() function to get the string,
352     * then cache it in #cachedDisassembly.  If the disassembly
353     * should not be cached, this function should be overridden directly.
354     */
355    virtual const std::string &disassemble(Addr pc,
356                                           const SymbolTable *symtab = 0) const
357    {
358        if (!cachedDisassembly)
359            cachedDisassembly =
360                new std::string(generateDisassembly(pc, symtab));
361
362        return *cachedDisassembly;
363    }
364
365    /// Decoded instruction cache type.
366    /// For now we're using a generic hash_map; this seems to work
367    /// pretty well.
368    typedef m5::hash_map<MachInst, StaticInstPtr<ISA> > DecodeCache;
369
370    /// A cache of decoded instruction objects.
371    static DecodeCache decodeCache;
372
373    /**
374     * Dump some basic stats on the decode cache hash map.
375     * Only gets called if DECODE_CACHE_HASH_STATS is defined.
376     */
377    static void dumpDecodeCacheStats();
378
379    /// Decode a machine instruction.
380    /// @param mach_inst The binary instruction to decode.
381    /// @retval A pointer to the corresponding StaticInst object.
382    static
383    StaticInstPtr<ISA> decode(MachInst mach_inst)
384    {
385#ifdef DECODE_CACHE_HASH_STATS
386        // Simple stats on decode hash_map.  Turns out the default
387        // hash function is as good as anything I could come up with.
388        const int dump_every_n = 10000000;
389        static int decodes_til_dump = dump_every_n;
390
391        if (--decodes_til_dump == 0) {
392            dumpDecodeCacheStats();
393            decodes_til_dump = dump_every_n;
394        }
395#endif
396
397        typename DecodeCache::iterator iter = decodeCache.find(mach_inst);
398        if (iter != decodeCache.end()) {
399            return iter->second;
400        }
401
402        StaticInstPtr<ISA> si = ISA::decodeInst(mach_inst);
403        decodeCache[mach_inst] = si;
404        return si;
405    }
406};
407
408typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
409
410/// Reference-counted pointer to a StaticInst object.
411/// This type should be used instead of "StaticInst<ISA> *" so that
412/// StaticInst objects can be properly reference-counted.
413template <class ISA>
414class StaticInstPtr : public RefCountingPtr<StaticInst<ISA> >
415{
416  public:
417    /// Constructor.
418    StaticInstPtr()
419        : RefCountingPtr<StaticInst<ISA> >()
420    {
421    }
422
423    /// Conversion from "StaticInst<ISA> *".
424    StaticInstPtr(StaticInst<ISA> *p)
425        : RefCountingPtr<StaticInst<ISA> >(p)
426    {
427    }
428
429    /// Copy constructor.
430    StaticInstPtr(const StaticInstPtr &r)
431        : RefCountingPtr<StaticInst<ISA> >(r)
432    {
433    }
434
435    /// Construct directly from machine instruction.
436    /// Calls StaticInst<ISA>::decode().
437    StaticInstPtr(typename ISA::MachInst mach_inst)
438        : RefCountingPtr<StaticInst<ISA> >(StaticInst<ISA>::decode(mach_inst))
439    {
440    }
441
442    /// Convert to pointer to StaticInstBase class.
443    operator const StaticInstBasePtr()
444    {
445        return this->get();
446    }
447};
448
449#endif // __CPU_STATIC_INST_HH__
450