static_inst.cc revision 7720
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 */ 31 32#include <iostream> 33#include "cpu/static_inst.hh" 34#include "sim/core.hh" 35 36StaticInstPtr StaticInst::nullStaticInstPtr; 37 38// Define the decode cache hash map. 39StaticInst::DecodeCache StaticInst::decodeCache; 40StaticInst::AddrDecodeCache StaticInst::addrDecodeCache; 41StaticInst::cacheElement StaticInst::recentDecodes[2]; 42 43using namespace std; 44 45StaticInst::~StaticInst() 46{ 47 if (cachedDisassembly) 48 delete cachedDisassembly; 49} 50 51void 52StaticInst::dumpDecodeCacheStats() 53{ 54 cerr << "Decode hash table stats @ " << curTick << ":" << endl; 55 cerr << "\tnum entries = " << decodeCache.size() << endl; 56 cerr << "\tnum buckets = " << decodeCache.bucket_count() << endl; 57 vector<int> hist(100, 0); 58 int max_hist = 0; 59 for (int i = 0; i < decodeCache.bucket_count(); ++i) { 60 int count = decodeCache.elems_in_bucket(i); 61 if (count > max_hist) 62 max_hist = count; 63 hist[count]++; 64 } 65 for (int i = 0; i <= max_hist; ++i) { 66 cerr << "\tbuckets of size " << i << " = " << hist[i] << endl; 67 } 68} 69 70bool 71StaticInst::hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc, 72 TheISA::PCState &tgt) const 73{ 74 if (isDirectCtrl()) { 75 tgt = branchTarget(pc); 76 return true; 77 } 78 79 if (isIndirectCtrl()) { 80 tgt = branchTarget(tc); 81 return true; 82 } 83 84 return false; 85} 86 87StaticInstPtr 88StaticInst::fetchMicroop(MicroPC upc) const 89{ 90 panic("StaticInst::fetchMicroop() called on instruction " 91 "that is not microcoded."); 92} 93 94TheISA::PCState 95StaticInst::branchTarget(const TheISA::PCState &pc) const 96{ 97 panic("StaticInst::branchTarget() called on instruction " 98 "that is not a PC-relative branch."); 99 M5_DUMMY_RETURN; 100} 101 102TheISA::PCState 103StaticInst::branchTarget(ThreadContext *tc) const 104{ 105 panic("StaticInst::branchTarget() called on instruction " 106 "that is not an indirect branch."); 107 M5_DUMMY_RETURN; 108} 109 110const string & 111StaticInst::disassemble(Addr pc, const SymbolTable *symtab) const 112{ 113 if (!cachedDisassembly) 114 cachedDisassembly = new string(generateDisassembly(pc, symtab)); 115 116 return *cachedDisassembly; 117} 118